公开(公告)号：US11849005B2

公开(公告)日：2023-12-19

申请号：US18076051

申请日：2022-12-06

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  SYSGEAR CO., LTD.

Inventor： Kwang-Won Koh ,  Kang-Ho Kim ,  Chang-Dae Kim ,  Tae-Hoon Kim ,  Sang-Ho Eom

IPC: H04L67/568 ,  G06F9/455 ,  H04L67/60

CPC classification number: H04L67/568 ,  G06F9/45558 ,  H04L67/60 ,  G06F2009/45595

Abstract: Disclosed herein are a method and apparatus for accelerating network transmission in a memory-disaggregated environment. The method for accelerating network transmission in a memory-disaggregated environment includes copying transmission data to a transmission buffer of the computing node, when a page fault occurs during copy of the transmission data, identifying a location at which the transmission data is stored, setting a node in which a largest amount of transmission data is stored as a transmission node, and sending a transmission command to the transmission node.

公开(公告)号：US12153525B2

公开(公告)日：2024-11-26

申请号：US18126229

申请日：2023-03-24

Applicant: Electronics and Telecommunications Research Institute ,  SYSGEAR CO., LTD.

Inventor： Tae-Hoon Kim ,  Kwang-Won Koh ,  Kang-Ho Kim ,  Chang-Dae Kim ,  Sang-Ho Eom

IPC: G06F12/0862 ,  G06F12/0864

Abstract: Disclosed herein are a method and apparatus for verifying integrity in a memory-disaggregated environment. The method for verifying integrity in a memory-disaggregated environment includes receiving write data and multiple hash values generated based on write data from a remote memory, and verifying integrity of the write data based on the write data and the hash values, wherein verifying the integrity of the write data comprises selecting a hash value for the integrity verification based on an access latency of the remote memory.

公开(公告)号：US12223186B2

公开(公告)日：2025-02-11

申请号：US18126232

申请日：2023-03-24

Applicant: Electronics and Telecommunications Research Institute ,  SYSGEAR CO., LTD.

Inventor： Chang-Dae Kim ,  Kwang-Won Koh ,  Kang-Ho Kim ,  Tae-Hoon Kim ,  Sang-Ho Eom

IPC: G06F3/06

Abstract: Disclosed herein is a method for memory management in a memory disaggregation environment. The method includes generating virtual memory based on multiple first memory devices, determining whether a condition for allocation acceleration is satisfied by the first memory devices, and allocating a memory page to the first memory devices based on whether the condition for allocation acceleration is satisfied.

公开(公告)号：US20250147663A1

公开(公告)日：2025-05-08

申请号：US18935895

申请日：2024-11-04

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Chang-Dae KIM ,  Kwang-Won Koh ,  Tae-Hoon Kim ,  Eun-Ji Pak ,  Yeon-Jeong Jeong

IPC: G06F3/06

Abstract: Disclosed herein is an apparatus and method for processing write-on-copy for supporting a fork in a memory disaggregation system. The method includes, when a child process is generated in the event of a fork, processing the fork by copying a page table for disaggregated memory of a parent process to the child process and setting write protection on a page of the disaggregated memory; and processing write access to the write-protected page. Processing the write access may use at least one of a first handler corresponding to access to the write-protected page mapped to the page table, or a second handler corresponding to the write access to the write-protected page that is not mapped to the page table, or a combination thereof.