公开(公告)号：US20150143010A1

公开(公告)日：2015-05-21

申请号：US14270631

申请日：2014-05-06

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jeong Ho SON ,  Yun Won Choi

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: In a real-time embedded system, if a higher-level interrupt having a higher priority than a lower-level interrupt being processed occurs, the lower-level interrupt is stopped from being processed and the higher-level interrupt is processed. Upon completion of the processing of the higher-level interrupt, delay information about the lower-level interrupt is recorded in a compensation timer register corresponding to the lower-level interrupt, and when the processing is stopped, the lower-level interrupt is restarted. Upon completion of the processing of the lower-level interrupt, the next period of the lower-level interrupt is adjusted based on the delay information recorded in the compensation timer register to compensate for the delay.

Abstract translation: 在实时嵌入式系统中，如果具有比正在处理的较低级别中断更高优先级的更高级别的中断，则下级中断将被停止处理，并且处理较高级别的中断。 在完成上级中断处理完成后，关于下位中断的延迟信息被记录在与下级中断相对应的补偿定时器寄存器中，当处理停止时，下级中断重新启动。 在完成下级中断处理后，根据记录在补偿定时器寄存器中的延迟信息来调整下一级中断的下一个周期以补偿延迟。