公开(公告)号：US20120057606A1

公开(公告)日：2012-03-08

申请号：US12880030

申请日：2010-09-10

申请人： Delong Cui ,  Afshin Momtaz ,  Jun Cao

发明人： Delong Cui ,  Afshin Momtaz ,  Jun Cao

IPC分类号： H04J3/06

CPC分类号： H04J3/047

摘要： According to an example embodiment, a circuit may include a first pair of differential input transistors, each coupled between at least an associated first positive clock transistor and ground; the first positive clock transistors coupled between differential output nodes and the differential input transistors associated with the first positive clock transistors, the first positive clock transistors being configured to respond to a positive input from a clock; a first inductor coupled between the differential output nodes and a voltage source; a second pair of differential input transistors, each coupled between at least an associated first negative clock transistor and ground; the first negative clock transistors coupled between the differential output nodes and the differential input transistors associated with the first negative clock transistors, the first negative clock transistors being configured to respond to a negative input from the clock; and the differential output nodes coupled between the first inductor, the first positive clock transistors, and the first negative clock transistors.

摘要翻译： 根据示例实施例，电路可以包括第一对差分输入晶体管，每个差分输入晶体管耦合在至少相关联的第一正时钟晶体管和地之间; 耦合在差分输出节点和与第一正时钟晶体管相关联的差分输入晶体管之间的第一正时钟晶体管，第一正时钟晶体管被配置为响应来自时钟的正输入; 耦合在所述差分输出节点和电压源之间的第一电感器; 第二对差分输入晶体管，每个耦合在至少相关联的第一负时钟晶体管和地之间; 耦合在差分输出节点和与第一负时钟晶体管相关联的差分输入晶体管之间的第一负时钟晶体管，第一负时钟晶体管被配置为响应来自时钟的负输入; 以及耦合在第一电感器，第一正时钟晶体管和第一负时钟晶体管之间的差分输出节点。

公开(公告)号：US20120326788A1

公开(公告)日：2012-12-27

申请号：US13166592

申请日：2011-06-22

申请人： Delong Cui ,  Afshin Momtaz ,  Jun Cao

发明人： Delong Cui ,  Afshin Momtaz ,  Jun Cao

IPC分类号： H03F3/16 ,  H03F3/04

CPC分类号： H03F3/16 ,  H03F1/42 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/336 ,  H03F2200/423 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45702 ,  H03F2203/45706

摘要： There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

摘要翻译： 为高速收发器提供了高带宽电路。 该电路可以包括组合电容器分离，电感树结构和各种带宽扩展技术的放大器，例如并联峰值，串联峰值和T形线圈峰值，以支持45Gbs / s及以上的数据速率，同时减少数据抖动。 电感树结构的电感元件还可以包括高阻抗传输线，从而简化了实现。 此外，电感器和t-线圈的容易识别的金属结构，负载电容器的相等分配以及对称的电感树结构可以简化收发器实现，但不限于时钟数据恢复电路。

公开(公告)号：US08731098B2

公开(公告)日：2014-05-20

申请号：US12882739

申请日：2010-09-15

申请人： Delong Cui ,  Afshin Momtaz ,  Jun Cao

发明人： Delong Cui ,  Afshin Momtaz ,  Jun Cao

IPC分类号： H04L27/04 ,  H04L27/20

CPC分类号： H04L7/0091 ,  H04L7/0008

摘要： A transmitting system includes a clock system and a data system. The clock system is configured to receive a clock having a first value and produce a control signal having a second, different value and an output clock having the first value. The data system is configured to receive data and the control signal and to align the data with the output clock, based on the control signal, to produce output data. The clock system includes a driver configured to produce the output clock, a divider configured to divide the received clock, and a phase interpolator configured to rotate the divided clock to produce the control signal. Also, the data is parallel data, and the data system includes a multiplexer configured to receive the parallel data and to use the control signal to serialize the parallel data as the aligned data and a driver configured to produce the output data.

摘要翻译： 发射系统包括时钟系统和数据系统。 时钟系统被配​​置为接收具有第一值的时钟并且产生具有第二不同值的控制信号和具有第一值的输出时钟。 数据系统被配置为基于控制信号接收数据和控制信号并使数据与输出时钟对准，以产生输出数据。 时钟系统包括配置成产生输出时钟的驱动器，被配置为对接收的时钟进行分频的分频器，以及被配置为旋转分频时钟以产生控制信号的相位内插器。 此外，数据是并行数据，并且数据系统包括被配置为接收并行数据并且使用控制信号将并行数据串行化为对准数据的多路复用器和被配置为产生输出数据的驱动器。

公开(公告)号：US08451058B2

公开(公告)日：2013-05-28

申请号：US13166592

申请日：2011-06-22

申请人： Delong Cui ,  Afshin Momtaz ,  Jun Cao

发明人： Delong Cui ,  Afshin Momtaz ,  Jun Cao

IPC分类号： H03F3/16 ,  H03F3/04

CPC分类号： H03F3/16 ,  H03F1/42 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/336 ,  H03F2200/423 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45702 ,  H03F2203/45706

摘要： There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

公开(公告)号：US07973681B2

公开(公告)日：2011-07-05

申请号：US12567841

申请日：2009-09-28

申请人： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

发明人： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

IPC分类号： H03M7/12

CPC分类号： H04L25/0276 ,  H03M5/04 ,  H04L25/0274 ,  H04L25/0282 ,  H04L25/0284

摘要： A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

摘要翻译： 门控逻辑接收非归零（NRZ）输入信号，并且在NRZ工作模式下将NRZ输入信号耦合为NRZ输出信号，并将NRZ输入信号转换为零（ RZ）输出信号。 耦合到门控逻辑的电路接收时钟信号并将时钟信号耦合到门控逻辑，以将RZ输入信号转换为RZ工作模式的RZ输出信号。 在NRZ工作模式下，电路解耦时钟信号，并在门控逻辑上放置预定的信号状态，以通过NRZ输入信号作为NRZ输出信号。 电路接收选择信号以在NRZ和RZ工作模式之间进行选择，并通过控制门控逻辑的时钟信号获得NRZ和RZ模式。

公开(公告)号：US20110074610A1

公开(公告)日：2011-03-31

申请号：US12567841

申请日：2009-09-28

申请人： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

发明人： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

IPC分类号： H03M7/12

CPC分类号： H04L25/0276 ,  H03M5/04 ,  H04L25/0274 ,  H04L25/0282 ,  H04L25/0284

摘要： A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

摘要翻译： 门控逻辑接收非归零（NRZ）输入信号，并且在NRZ工作模式下将NRZ输入信号耦合为NRZ输出信号，并将NRZ输入信号转换为零（ RZ）输出信号。 耦合到门控逻辑的电路接收时钟信号并将时钟信号耦合到门控逻辑，以将RZ输入信号转换为RZ工作模式的RZ输出信号。 在NRZ工作模式下，电路解耦时钟信号，并在门控逻辑上放置预定的信号状态，以通过NRZ输入信号作为NRZ输出信号。 该电路接收选择信号以在NRZ和RZ工作模式之间进行选择，并通过控制门控逻辑的时钟信号获得NRZ和RZ模式。