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公开(公告)号：US20090243687A1
公开(公告)日：2009-10-01
申请号：US12060795
申请日：2008-04-01
CPC分类号： H03K3/0375
摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.
摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器显示出通过条件降低的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。
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2.发明授权Apparatus for using metastability-hardened storage circuits in logic devices and associated methods 有权在逻辑器件和相关方法中使用亚稳态硬化存储电路的装置公开(公告)号：US07977975B1
公开(公告)日：2011-07-12
申请号：US12563088
申请日：2009-09-18
IPC分类号： H03K19/00
CPC分类号： H03K3/356008 , H03K3/0375 , H03K19/00315 , H03K19/17764
摘要： An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.
摘要翻译： 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。
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3.发明授权公开(公告)号：US08508254B2
公开(公告)日：2013-08-13
申请号：US13149774
申请日：2011-05-31
IPC分类号： H03K19/00
CPC分类号： H03K3/356008 , H03K3/0375 , H03K19/00315 , H03K19/17764
摘要： An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.
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公开(公告)号：US08253463B1
公开(公告)日：2012-08-28
申请号：US12721488
申请日：2010-03-10
IPC分类号： H03K5/04
CPC分类号： H03K3/017 , H03K3/0375 , H03K5/131
摘要： Integrated circuits with pulse latches are provided. Pulse latches are controlled by clock pulse signals. The clock pulse signals are generated by pulse generators. The pulse generators are controlled by adaptive pulse width control circuitry to provide clock pulse signals with a minimum pulse width and with sufficient margin to tolerate for process, voltage, and temperature variations. The pulse width control circuitry may include a replica pulse generator, a test data generation circuit, a test latch, and a pulse width calibration circuit. The replica pulse generator controls the test latch. The test latch may attempt to latch the test data. The pulse width control circuit may determine if the test latch properly latches the test data with the given pulse width. The pulse width control circuit adjusts the pulse generator dynamically to provide a minimized pulse width.
摘要翻译： 提供具有脉冲锁存器的集成电路。 脉冲锁存器由时钟脉冲信号控制。 时钟脉冲信号由脉冲发生器产生。 脉冲发生器由自适应脉冲宽度控制电路控制，以提供具有最小脉冲宽度的时钟脉冲信号，并具有足够的裕度以容忍过程，电压和温度变化。 脉冲宽度控制电路可以包括复制脉冲发生器，测试数据产生电路，测试锁存器和脉冲宽度校准电路。 复制脉冲发生器控制测试锁存器。 测试锁存器可以尝试锁存测试数据。 脉冲宽度控制电路可以确定测试锁存器是否以给定的脉冲宽度适当地锁存测试数据。 脉冲宽度控制电路动态地调节脉冲发生器以提供最小的脉冲宽度。
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公开(公告)号：US08115530B2
公开(公告)日：2012-02-14
申请号：US12976752
申请日：2010-12-22
IPC分类号： H03K3/00
CPC分类号： H03K3/0375
摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.
摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器显示出通过条件降低的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。
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6.发明申请APPARATUS FOR USING METASTABILITY-HARDENED STORAGE CIRCUITS IN LOGIC DEVICES AND ASSOCIATED METHODS 有权在逻辑设备和相关方法中使用可扩展性硬化存储电路的设备公开(公告)号：US20110227625A1
公开(公告)日：2011-09-22
申请号：US13149774
申请日：2011-05-31
IPC分类号： H03K3/02
CPC分类号： H03K3/356008 , H03K3/0375 , H03K19/00315 , H03K19/17764
摘要： An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.
摘要翻译： 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。
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公开(公告)号：US07872512B2
公开(公告)日：2011-01-18
申请号：US12060795
申请日：2008-04-01
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.
摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器具有降低的竞争条件的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。
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公开(公告)号：US07746100B2
公开(公告)日：2010-06-29
申请号：US12111142
申请日：2008-04-28
IPC分类号： H03K19/177 , G06F7/42
CPC分类号： G06F7/506 , G06F2207/4812
摘要： Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a redundancy control signal. During manufacturing, the integrated circuitry may be tested. If a defect is identified on the integrated circuit, the redundancy control signal may be used in switching redundant circuitry into place bypassing the defect. The integrated circuit may contain an array of logic regions. Each logic region may contain adders and multiplexer circuitry for selectively combining the multiplexers to form larger adders. The multiplexer circuitry in each logic region may be controlled by propagate signals from the adders and by static redundancy control signals.
摘要翻译： 在包括冗余电路的集成电路上提供可配置加法器电路。 集成电路可以包含产生冗余控制信号的非易失性存储器和逻辑电路。 在制造期间，可以测试集成电路。 如果在集成电路上识别出缺陷，则冗余控制信号可用于将冗余电路切换到绕过缺陷的位置。 集成电路可以包含逻辑区域的阵列。 每个逻辑区域可以包含用于选择性地组合多路复用器以形成较大加法器的加法器和多路复用器电路。 每个逻辑区域中的复用器电路可以由来自加法器的传播信号和静态冗余控制信号来控制。
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公开(公告)号：US08427213B2
公开(公告)日：2013-04-23
申请号：US13347626
申请日：2012-01-10
IPC分类号： H03K3/00
CPC分类号： H03K3/0375
摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.
摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器显示出通过条件降低的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。
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公开(公告)号：US20110089974A1
公开(公告)日：2011-04-21
申请号：US12976752
申请日：2010-12-22
CPC分类号： H03K3/0375
摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.
摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器具有降低的竞争条件的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。
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