公开(公告)号：US4901259A

公开(公告)日：1990-02-13

申请号：US232269

申请日：1988-08-15

申请人： Daniel R. Watkins

发明人： Daniel R. Watkins

IPC分类号： G01R31/3183 ,  G06F11/26 ,  G06F17/50

CPC分类号： G01R31/318357 ,  G01R31/318307 ,  G06F11/261 ,  G06F17/5022

摘要： Disclosed is a simulation model which facilitates the "real-time" simulation of application specific integrated circuits (ASICs) in the actual digital computer system in which they will be incorporated. Significantly, this invention permits the emulation of an ASIC device, and thus does not require the fabrication of an actual physical specimen of that device. Instead, this invention permits the use of a software model which facilitates debugging of the ASIC device and permits effective generation of system test vectors. Such an approach facilitates the system-level testing of ASIC devices prior to fabrication, by permitting both the generation of system test vectors and the debugging of the internal behavior of such ASIC devices without limiting the flexibility, with respect to other devices in the system, of either simulating such devices in software or utilizing actual physical specimens of such devices.

摘要翻译： 公开了一种有助于实时数字计算机系统中专用集成电路（ASIC）的“实时”仿真的仿真模型。 重要的是，本发明允许仿真ASIC器件，因此不需要制造该器件的实际物理样本。 相反，本发明允许使用便于ASIC设备的调试并允许系统测试向量的有效产生的软件模型。 这样的方法通过允许系统测试向量的产生和这种ASIC设备的内部行为的调试，而不会限制系统中的其他设备的灵活性，有助于在制造之前对ASIC设备的系统级测试， 在软件中模拟这些设备或利用这些设备的实际物理样本。

公开(公告)号：US4779093A

公开(公告)日：1988-10-18

申请号：US836022

申请日：1986-03-04

申请人： Daniel R. Watkins

发明人： Daniel R. Watkins

IPC分类号： G06F13/42 ,  H04J3/02 ,  G08C15/00 ,  H04L7/00

CPC分类号： G06F13/4291

摘要： A bus interface system for communicating between a master bus interface and a plurality of slave bus interfaces includes a plurality of lines extending between the master unit and each of the slave units, the lines including a clock line containing clock signals, a gated clock line containing gated clock signals having a frequency which is a submultiple of the frequency of the clock signals, a data line, a command register line, an active line, and circuitry for exchanging data between the master unit and one of the slave units on the data line under the control of the other lines.

摘要翻译： 用于在主总线接口和多个从属总线接口之间进行通信的总线接口系统包括在主单元和每个从单元之间延伸的多条线，这些线包括包含时钟信号的时钟线，包含 门控时钟信号的频率是时钟信号的频率的一个倍数，数据线，命令寄存器线，有源线和用于在主单元和数据线上的一个从单元之间交换数据的电路 在其他线路的控制下。

公开(公告)号：US07024641B1

公开(公告)日：2006-04-04

申请号：US10119821

申请日：2002-04-10

申请人： Daniel R. Watkins

发明人： Daniel R. Watkins

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： The present invention provides an integrated circuit (IC). In one embodiment, the IC includes a substrate and a plurality of gate array blocks located on the substrate. Each of the blocks includes a programmable gate array (PGA) containing at least a portion of a circuit design in an interconnect layer thereof, and a field-programmable gate array (FPGA) coupled to the PGA and capable of containing a configuration that augments the portion of the circuit design. In this embodiment, the PGA and the FPGA cooperate to effect the circuit design. In another aspect, the present invention provides a method of designing an IC. In yet another aspect, the present invention provides a method of manufacturing ICs.

摘要翻译： 本发明提供一种集成电路（IC）。 在一个实施例中，IC包括基板和位于基板上的多个栅极阵列块。 每个块包括在其互连层中包含电路设计的至少一部分的可编程门阵列（PGA）和耦合到PGA的现场可编程门阵列（FPGA），并且能够包含增加 部分电路设计。 在本实施例中，PGA和FPGA协同实现电路设计。 另一方面，本发明提供一种IC的设计方法。 在另一方面，本发明提供了一种制造IC的方法。

公开(公告)号：US5666289A

公开(公告)日：1997-09-09

申请号：US980492

申请日：1992-11-23

申请人： Daniel R. Watkins

发明人： Daniel R. Watkins

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A system for designing an integrated circuit with multiple functions is disclosed. The system creates a set of files defining a structure for a plurality of functions existing within one integrated circuit. Floorplanning modifications are then permissible within any functional block, as well as from one functional block to another since the files for each integrated circuit chip are reconfigureable upon modification. The subject invention also provides for floorplanning modifications involving multiple integrated circuit chips wherein any one functional block may be moved from one integrated circuit chip to another to achieve better optimization with less restrictions.

摘要翻译： 公开了一种用于设计具有多种功能的集成电路的系统。 该系统创建一组定义一个集成电路内存在的多个功能的结构的文件。 在任何功能块以及从一个功能块到另一个功能块之间，可以进行布局规划修改，因为每个集成电路芯片的文件在修改后都是可重新配置的。 本发明还提供涉及多个集成电路芯片的布局规划修改，其中任何一个功能块可以从一个集成电路芯片移动到另一个，以通过较少的限制来实现更好的优化。

公开(公告)号：US07657807B1

公开(公告)日：2010-02-02

申请号：US11167248

申请日：2005-06-27

申请人： Daniel R. Watkins ,  Hunter S. Donahue ,  Thomas Alan Ziaja

发明人： Daniel R. Watkins ,  Hunter S. Donahue ,  Thomas Alan Ziaja

IPC分类号： G01R31/28

CPC分类号： G01R31/318594

摘要： An integrated circuit including embedded test functionality. An integrated circuit may include a plurality of processor cores each configured to execute instructions, and a test access port configured to interface circuits included within the integrated circuit with a test environment external to the integrated circuit for testing of the circuits. The test access port may include virtualization logic configured to allow a first set of instructions executing on the given processor core to control activity of the test access port for testing of the circuits. In one embodiment, the circuits may be accessible for testing via a plurality of scan chains, wherein the scan chains and the test access port are compliant with a version of Joint Test Access Group (JTAG) standard IEEE 1149, and wherein the test access port includes a Test Data In (TDI) pin, a Test Data Out (TDO) pin, and a Test Clock (TCK) pin.

摘要翻译： 包含嵌入式测试功能的集成电路。 集成电路可以包括被配置为执行指令的多个处理器核心以及被配置为将集成电路中包括的电路与用于电路测试的集成电路外部的测试环境接合的测试访问端口。 测试访问端口可以包括虚拟化逻辑，其被配置为允许在给定处理器核上执行的第一组指令来控制用于测试电路的测试访问端口的活动。 在一个实施例中，电路可以通过多个扫描链进行测试，其中扫描链和测试访问端口符合联合测试访问组（JTAG）标准IEEE 1149的版本，并且其中测试访问端口 包括测试数据输入（TDI）引脚，测试数据输出（TDO）引脚和测试时钟（TCK）引脚。

公开(公告)号：US06769107B1

公开(公告)日：2004-07-27

申请号：US10005062

申请日：2001-12-03

申请人： Daniel R. Watkins

发明人： Daniel R. Watkins

IPC分类号： G06F175035

CPC分类号： G06F17/5054

摘要： A method implements a change to a circuit design for a system formed on a semiconductor chip, the circuit design including at least one circuit core. The method includes providing in the circuit design at least one field programmable gate array (FPGA) core, extracting an incremental change to the circuit design by comparing a new resister-transfer-level (RTL) design and an old RTL design for the system, synthesizing the incremental change into a netlist for the at least one FPGA core, generating new metal layer interconnections so as to provide an input and an output for the at least one FPGA core in accordance with the incremental change, and programming the at least one FPGA core in accordance with the netlist. The at least one FPGA core is provided in an otherwise unused area of the chip.

摘要翻译： 一种方法实现了对形成在半导体芯片上的系统的电路设计的改变，该电路设计包括至少一个电路核心。 该方法包括在电路设计中提供至少一个现场可编程门阵列（FPGA）核心，通过比较新的电阻传输级（RTL）设计和系统的旧RTL设计来提取电路设计的增量变化， 将所述增量变化合成为所述至少一个FPGA核心的网表，生成新的金属层互连，以便根据增量变化为所述至少一个FPGA内核提供输入和输出，以及编程所述至少一个FPGA 核心按照网表。 至少一个FPGA核心被提供在芯片的另外未使用的区域中。

公开(公告)号：US5544067A

公开(公告)日：1996-08-06

申请号：US77294

申请日：1993-06-14

申请人： Michael D. Rostoker ,  Carlos Dangelo ,  Daniel R. Watkins

发明人： Michael D. Rostoker ,  Carlos Dangelo ,  Daniel R. Watkins

IPC分类号： G01R31/317 ,  G01R31/3183 ,  G06F11/26 ,  G06F17/50

CPC分类号： G01R31/318357 ,  G01R31/31704 ,  G01R31/318364 ,  G01R31/318378 ,  G06F11/261 ,  G06F17/5022 ,  G06F17/5045

摘要： A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations. Schematic diagram and simulation displays showing those portions of the electronic system and simulated signal patterns which are related to the design rule violations are used to help the user identify and appropriately correct problems in the design.

摘要翻译： 一种用于电子系统的交互式设计，综合和仿真的系统，允许用户通过以诸如VHDL或图形输入的高级语言的行为模型的规范来设计系统。 用户可以在单个显示窗口上同时查看完整或部分模拟和设计结果。 综合过程使用系统的技术来绘制和强化嵌入原始高级描述意图的语义的一致性。 设计活动通常是在各种级别的设计表示上进行的一系列转换。 在每个层次上，可以以原理图形式对设计进行模拟和审查。 模拟结果可以与它们对应的图上的信号线紧邻显示。 在一个实施例中，设计规则违规由专家系统处理，以建议可能的更正或改变设计，这将消除设计规则违规。 示意图和模拟显示显示了与设计规则违规相关的电子系统部分和模拟信号模式的部分，用于帮助用户识别和适当地纠正设计中的问题。

公开(公告)号：US07650625B2

公开(公告)日：2010-01-19

申请号：US10320046

申请日：2002-12-16

申请人： Daniel R. Watkins

发明人： Daniel R. Watkins

IPC分类号： H04N7/18 ,  H04N7/173 ,  H04N7/16

CPC分类号： H04N21/4508 ,  H04N5/782 ,  H04N21/4334 ,  H04N21/4394 ,  H04N21/44008 ,  H04N21/4532 ,  H04N21/4828

摘要： A settop box system for capturing and controlling live and recorded audio and video content. The system records digital and analog data from video and audio content, such as in a home entertainment center. The system records data from the content as specified and the data may be sequenced into clips that can be searched and indexed. A user may create comparison programs that allow searches of either pre-recorded or incoming content to be performed. In addition, the program allows editing of recorded programs, such as filtering of audio content or overlaying a video program with a different audio background. Multiple audio and video feeds may be handled simultaneously and the program's functions may be executed without viewing of the content being manipulated. The recorded content may also be indexed and even clips of the content may be indexed.

摘要翻译： 一种用于捕获和控制实况和录制的音频和视频内容的机顶盒系统。 该系统记录来自视频和音频内容的数字和模拟数据，例如在家庭娱乐中心。 系统从指定的内容记录数据，并且数据可以被排序成可被搜索和索引的剪辑。 用户可以创建允许执行预记录或传入内容的搜索的比较程序。 此外，该程序允许编辑记录的节目，例如滤波音频内容或覆盖具有不同音频背景的视频节目。 可以同时处理多个音频和视频馈送，并且可以执行节目的功能而不查看被操纵的内容。 记录的内容也可以被索引，并且甚至可以索引内容的剪辑。

公开(公告)号：US06775798B2

公开(公告)日：2004-08-10

申请号：US09996042

申请日：2001-11-28

申请人： Daniel R. Watkins

发明人： Daniel R. Watkins

IPC分类号： G01R3128

CPC分类号： G01R31/318314 ,  G01R31/3177 ,  G01R31/318342 ,  G11C29/56004

摘要： An apparatus and method for using the apparatus for reducing analysis time of integrated circuits. The apparatus includes an integrated logic analyzer inserted in a substrate containing the integrated circuit and means for accelerating circuit analysis using the integrated logic analyzer. The means may be selected from the group consisting of a high speed sampling circuit coupled to the integrated logic analyzer and an on-board circuit testing and analysis apparatus including the integrated logic analyzer. Use of the apparatus enables lower production costs by speeding up circuit analysis as well as providing analysis of high speed circuits in a cost effective manner.

摘要翻译： 一种用于减少集成电路分析时间的装置和方法。 该装置包括插入到包含集成电路的基板中的集成逻辑分析器和用于使用集成逻辑分析器加速电路分析的装置。 该装置可以选自耦合到集成逻辑分析器的高速采样电路和包括集成逻辑分析仪的车载电路测试和分析装置。 使用该装置可以通过加速电路分析并以成本有效的方式提供高速电路的分析来降低生产成本。

公开(公告)号：US06745358B1

公开(公告)日：2004-06-01

申请号：US09997757

申请日：2001-11-30

申请人： Daniel R. Watkins

发明人： Daniel R. Watkins

IPC分类号： G01R3128

CPC分类号： G01R31/31703 ,  G01R31/318342 ,  G01R31/31835 ,  G01R31/318378 ,  G01R31/318566 ,  G01R31/318583

摘要： A tool and method for increasing fault coverage of an integrated circuit. The tool includes a key nodes detection device for matching key nodes to a fault grading report list of undetected nodes, a multi-sites selection device for reading a layout file of available multi unit sites for the integrated circuit, a site matching device for matching available multi-unit sites to key undetected nodes, and a netlist generation device for building logic functions in the available multi-unit sites for connection to the key undetected nodes. Use of the invention enables increased fault coverage of integrated circuit circuits for little or no added expense.

摘要翻译： 一种增加集成电路故障覆盖的工具和方法。 该工具包括用于将关键节点匹配到未检测节点的故障分级报告列表的关键节点检测装置，用于读取用于集成电路的可用多单元站点的布局文件的多站点选择装置，用于匹配可用的站点匹配装置 多单元站点到关键未检测节点，以及网表生成设备，用于在可用的多单元站点中构建逻辑功能，用于连接到未被检测到的关键节点。 使用本发明可以增加集成电路电路的故障覆盖率，甚至不需要增加费用。