公开(公告)号：US20120217559A1

公开(公告)日：2012-08-30

申请号：US13369900

申请日：2012-02-09

申请人： Daeik Kim ,  Sooho Shin

发明人： Daeik Kim ,  Sooho Shin

IPC分类号： H01L27/108

CPC分类号： H01L27/10855 ,  H01L27/10876

摘要： A semiconductor memory device includes an active region protruding from a substrate. The active region includes first and second doped regions therein and a trench therein separating the first and second doped regions. A buried gate structure extends in a first direction along the trench between first and second opposing sidewalls thereof. A conductive interconnection plug is provided on the first doped region adjacent the first sidewall of the trench, and a conductive landing pad is provided on the second doped region adjacent the second sidewall of the trench. The landing pad has a width greater than that of the second doped region of the active region along the first direction. A conductive storage node contact plug is provided on the landing pad opposite the second doped region. The storage node contact plug has a narrower width than the landing pad along the first direction.

摘要翻译： 半导体存储器件包括从衬底突出的有源区。 有源区域包括其中的第一和第二掺杂区域以及在其中分隔第一和第二掺杂区域的沟槽。 掩埋栅极结构沿着第一和第二相对侧壁之间的沟槽在第一方向上延伸。 在与沟槽的第一侧壁相邻的第一掺杂区域上提供导电互连插头，并且在邻近沟槽的第二侧壁的第二掺杂区域上提供导电接合焊盘。 着陆焊盘的宽度大于沿着第一方向的有源区域的第二掺杂区域的宽度。 导电存储节点接触插头设置在与第二掺杂区域相对的着陆焊盘上。 存储节点接触插头沿着第一方向具有比着陆焊盘窄的宽度。

公开(公告)号：US08878273B2

公开(公告)日：2014-11-04

申请号：US13369900

申请日：2012-02-09

申请人： Daeik Kim ,  Sooho Shin

发明人： Daeik Kim ,  Sooho Shin

IPC分类号： H01L29/94 ,  H01L27/108

CPC分类号： H01L27/10855 ,  H01L27/10876

摘要： A semiconductor memory device includes an active region protruding from a substrate. The active region includes first and second doped regions therein and a trench therein separating the first and second doped regions. A buried gate structure extends in a first direction along the trench between first and second opposing sidewalls thereof. A conductive interconnection plug is provided on the first doped region adjacent the first sidewall of the trench, and a conductive landing pad is provided on the second doped region adjacent the second sidewall of the trench. The landing pad has a width greater than that of the second doped region of the active region along the first direction. A conductive storage node contact plug is provided on the landing pad opposite the second doped region. The storage node contact plug has a narrower width than the landing pad along the first direction.

摘要翻译： 半导体存储器件包括从衬底突出的有源区。 有源区域包括其中的第一和第二掺杂区域以及在其中分隔第一和第二掺杂区域的沟槽。 掩埋栅极结构沿着第一和第二相对侧壁之间的沟槽在第一方向上延伸。 在与沟槽的第一侧壁相邻的第一掺杂区域上提供导电互连插头，并且在邻近沟槽的第二侧壁的第二掺杂区域上提供导电接合焊盘。 着陆焊盘的宽度大于沿着第一方向的有源区域的第二掺杂区域的宽度。 导电存储节点接触插头设置在与第二掺杂区域相对的着陆焊盘上。 存储节点接触插头沿着第一方向具有比着陆焊盘窄的宽度。