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公开(公告)号：US20240256930A1
公开(公告)日：2024-08-01
申请号：US18514482
申请日：2023-11-20
申请人： D-WAVE SYSTEMS INC.
发明人： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
摘要： A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号：US11681940B2
公开(公告)日：2023-06-20
申请号：US17379172
申请日：2021-07-19
申请人： D-WAVE SYSTEMS INC.
发明人： Andrew Douglas King , Alexandre Fréchette , Evgeny A. Andriyash , Trevor Michael Lanting , Emile M. Hoskinson , Mohammad H. Amin
IPC分类号： G06N10/00 , G06F15/163
CPC分类号： G06N10/00 , G06F15/163
摘要： Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.
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公开(公告)号：US11295225B2
公开(公告)日：2022-04-05
申请号：US16029026
申请日：2018-07-06
申请人： D-Wave Systems Inc.
摘要： Passive and actives approaches to mitigating the effects of spin-bath polarization are described and illustrated. Such may, for example, include at least partially depolarizing the spin-bath polarization, for instance by: performing an annealing cycle by the quantum processor to generate a final state of a qubit of the quantum processor; flipping the final state of the qubit of the quantum processor to an opposite state; and latching the qubit in the opposite state for a predetermined duration.
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公开(公告)号：US20180330264A1
公开(公告)日：2018-11-15
申请号：US15771606
申请日：2016-10-27
申请人： D-WAVE SYSTEMS INC.
IPC分类号： G06N99/00 , G06F15/163
CPC分类号： G06N99/002
摘要： Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.
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公开(公告)号：US20150346291A1
公开(公告)日：2015-12-03
申请号：US14462200
申请日：2014-08-18
申请人： D-Wave Systems Inc.
发明人： Trevor Michael Lanting , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Sergey V. Uchaykin , Andrew Brock Wilson , Mark Johnson
IPC分类号： G01R33/035 , G01R33/00
CPC分类号： G01R33/0354 , G01R33/0017 , G01R33/0094
摘要： SQUIDs may detect local magnetic fields. SQUIDS of varying sizes, and hence sensitivities may detect different magnitudes of magnetic fields. SQUIDs may be oriented to detect magnetic fields in a variety of orientations, for example along an orthogonal reference frame of a chip or wafer. The SQUIDS may be formed or carried on the same chip or wafer as a superconducting processor (e.g., a superconducting quantum processor). Measurement of magnetic fields may permit compensation, for example allowing tuning of a compensation field via a compensation coil and/or a heater to warm select portions of a system. A SQIF may be implemented as a SQUID employing an unconventional grating structure. Successful fabrication of an operable SQIF may be facilitated by incorporating multiple Josephson junctions in series in each arm of the unconventional grating structure.
摘要翻译： SQUID可以检测局部磁场。 具有不同尺寸的SQUIDS，因此灵敏度可以检测不同的磁场强度。 SQUID可以被定向以检测各种取向中的磁场，例如沿着芯片或晶片的正交参考系。 SQUIDS可以与超导处理器（例如超导量子处理器）形成或携带在相同的芯片或晶片上。 磁场的测量可以允许补偿，例如允许通过补偿线圈和/或加热器对补偿场进行调谐以温暖系统的选择部分。 SQIF可以被实现为采用非常规光栅结构的SQUID。 可以通过将多个约瑟夫逊结串联在非常规光栅结构的每个臂中来促进可操作的SQIF的成功制造。
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6.发明申请公开(公告)号：US20150262073A1
公开(公告)日：2015-09-17
申请号：US14643180
申请日：2015-03-10
申请人： D-Wave Systems Inc.
CPC分类号： G06F17/00 , G06F15/82 , G06N99/002
摘要： Systems, devices, articles, methods, and techniques for advancing quantum computing by removing unwanted interactions in one or more quantum processor. One approach includes creating an updated plurality of programmable parameters based at least in part on a received value for the characteristic magnetic susceptibility of the qubit in the at least one quantum processor, and returning the updated plurality of programmable parameters. Examples programmable parameters include local biases, and coupling values characterizing the problem Hamilton. Also, for example, a quantum processor may be summarized as including a first loop of superconducting material, a first compound Josephson junction interrupting the first loop of superconducting material, a first coupler inductively coupled to the first loop of superconducting material, a second coupler inductively coupled to the first loop of superconducting material, and a second loop of superconducting material proximally placed to the first loop of superconducting material inductively coupled to the first coupler and the second coupler.
摘要翻译： 通过消除一个或多个量子处理器中的不需要的交互来推进量子计算的系统，设备，文章，方法和技术。 一种方法包括至少部分地基于所述至少一个量子处理器中的量子位的特征磁化率的接收值创建更新的多个可编程参数，以及返回更新的多个可编程参数。 示例可编程参数包括局部偏差和表征问题Hamilton的耦合值。 此外，例如，量子处理器可以总结为包括超导材料的第一环路，中断超导材料的第一环路的第一复合约瑟夫逊结，感应耦合到超导材料的第一环路的第一耦合器，感应地耦合到第二环路的第二耦合器 耦合到超导材料的第一回路，以及近端放置到感应耦合到第一耦合器和第二耦合器的超导材料的第一环路的第二回路的超导材料。
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公开(公告)号：US20230325695A1
公开(公告)日：2023-10-12
申请号：US18137271
申请日：2023-04-20
申请人： D-WAVE SYSTEMS INC.
发明人： Steven P. Reinhardt , Andrew D. King , Loren J. Swenson , Warren T.E. Wilkinson , Trevor Michael Lanting
IPC分类号： G06N10/00 , G05B19/042
CPC分类号： G06N10/00 , G05B19/042 , G05B2219/25071
摘要： Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
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公开(公告)号：US20200320424A1
公开(公告)日：2020-10-08
申请号：US16858108
申请日：2020-04-24
申请人： D-WAVE SYSTEMS INC.
发明人： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
摘要： A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号：US10789329B2
公开(公告)日：2020-09-29
申请号：US16673478
申请日：2019-11-04
申请人： D-WAVE SYSTEMS INC.
摘要： Systems, devices, articles, methods, and techniques for advancing quantum computing by removing unwanted interactions in one or more quantum processor. One approach includes creating an updated plurality of programmable parameters based at least in part on a received value for the characteristic magnetic susceptibility of the qubit in the at least one quantum processor, and returning the updated plurality of programmable parameters. Examples programmable parameters include local biases, and coupling values characterizing the problem Hamilton. Also, for example, a quantum processor may be summarized as including a first loop of superconducting material, a first compound Josephson junction interrupting the first loop of superconducting material, a first coupler inductively coupled to the first loop of superconducting material, a second coupler inductively coupled to the first loop of superconducting material, and a second loop of superconducting material proximally placed to the first loop of superconducting material inductively coupled to the first coupler and the second coupler.
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公开(公告)号：US20180219150A1
公开(公告)日：2018-08-02
申请号：US15503367
申请日：2015-08-12
申请人： D-Wave Systems Inc.
IPC分类号： H01L39/24 , H01L39/22 , H01L21/768
CPC分类号： H01L39/2493 , H01L21/76891 , H01L23/53285 , H01L27/18 , H01L39/223
摘要： Fabricating wiring layers above a Josephson junction multi-layer may include removing a part of the multilayer; depositing an insulating layer to overlie a part of the multilayer; and patterning the insulating layer to define a hole in the insulating layer. The method includes depositing a first superconducting wiring layer over a part of the insulating layer and within a portion of the hole. Further, insulating and wiring layers may be deposited and a topmost wiring layer defined. The method includes depositing a passivating layer to overlie the topmost wiring layer. Fabricating a superconducting integrated circuit comprising a hybrid dielectric system may include depositing a high-quality dielectric layer that overlies a superconducting feature. The method includes depositing a second dielectric layer that overlies at least part of the high-quality dielectric layer. The second dielectric layer can comprise a conventional dielectric material.
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