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    Masked gate logic for resistance to power analysis
    2.
    发明授权
    Masked gate logic for resistance to power analysis 有权

    公开(公告)号：US11386236B2

    公开(公告)日：2022-07-12

    申请号：US16427636

    申请日：2019-05-31

    Applicant: Cryptography Research, Inc.

    Inventor： Andrew John Leiserson ,  Mark Evan Marson ,  Megan Anneke Wachs

    IPC: G06F21/72 ,  G06F21/71 ,  G06F21/75 ,  H04L9/00

    Abstract: A method of and system for gate-level masking of secret data during a cryptographic process is described. A mask share is determined, wherein a first portion of the mask share includes a first number of zero-values and a second number of one-values, and a second portion of the mask share includes the first number of one-values and the second number of zero-values. Masked data values and the first portion of the mask share are input into a first portion of masked gate logic, and the masked data values and the second portion of the mask share are input into a second portion of the masked gate logic. A first output from the first portion of the masked gate logic and a second output from the second portion of the masked gate logic are identified, wherein either the first output or the second output is a zero-value.

    Configurator for secure feature and key manager
    4.
    发明授权
    Configurator for secure feature and key manager 有权
    用于安全功能和密钥管理器的配置器

    公开(公告)号：US09436848B2

    公开(公告)日：2016-09-06

    申请号：US14289274

    申请日：2014-05-28

    Applicant: Cryptography Research, Inc.

    Inventor： Daniel Beitel ,  Lauren Gao ,  Christopher Gori ,  Paul Carl Kocher ,  Ambuj Kumar ,  Andrew John Leiserson

    IPC: G06F11/30 ,  G06F21/76 ,  G06F21/57

    CPC classification number: G06F21/76 ,  G06F21/572

    Abstract: A computing device receives a feature name or key name for an integrated circuit comprising a security manager core and an additional component. At least one of a) the additional component is associated with the key name or b) a feature provided by the additional component is associated with the feature name. The computing device receives a specified number of bits associated with the feature name or the key name, and maps the feature name to a feature address space or the key name to a key interface of the security manager core based at on the specified number of bits. The computing device generates at least one hardware description logic (HDL) module based on the mapping, wherein the at least one HDL module is usable to configure the security manager core for delivery of payloads associated with the feature name or the key name to the additional component.

    Abstract translation: 计算设备接收包括安全管理器核心和附加组件的集成电路的功能名称或密钥名称。 a）附加组件中的至少一个与密钥名称相关联，或者b）由附加组件提供的特征与特征名称相关联。 计算设备接收与特征名称或密钥名称相关联的指定数量的位，并且基于指定的位数将特征名称映射到特征地址空间或密钥名称到安全管理器核心的密钥接口 。 所述计算设备基于所述映射生成至少一个硬件描述逻辑（HDL）模块，其中所述至少一个HDL模块可用于配置所述安全管理器核心，用于将与所述特征名称或所述密钥名称相关联的有效载荷传递到所述附加 零件。

    GATE-LEVEL MASKING
    5.
    发明申请
    GATE-LEVEL MASKING 有权
    门盖级屏蔽

    公开(公告)号：US20150169904A1

    公开(公告)日：2015-06-18

    申请号：US14565821

    申请日：2014-12-10

    Applicant: CRYPTOGRAPHY RESEARCH, INC.

    Inventor： Andrew John Leiserson ,  Mark Evan Marson ,  Megan Anneke Wachs

    IPC: G06F21/72 ,  G06F21/55

    CPC classification number: G06F21/72 ,  G06F21/71 ,  G06F21/755 ,  H04L9/003 ,  H04L2209/04 ,  H04L2209/12 ,  H04L2209/16

    Abstract: A method of and system for gate-level masking of secret data during a cryptographic process is described. A mask share is determined, wherein a first portion of the mask share includes a first number of zero-values and a second number of one-values, and a second portion of the mask share includes the first number of one-values and the second number of zero-values. Masked data values and the first portion of the mask share are input into a first portion of masked gate logic, and the masked data values and the second portion of the mask share are input into a second portion of the masked gate logic. A first output from the first portion of the masked gate logic and a second output from the second portion of the masked gate logic are identified, wherein either the first output or the second output is a zero-value.

    Abstract translation: 描述在密码处理期间秘密数据的门级掩蔽的方法和系统。 确定掩模共享，其中掩模共享的第一部分包括第一数量的零值和第二数量的一值，并且掩模共享的第二部分包括第一数量的一值，第二部分包括第二数量的一值 零值数。 掩蔽数据值和掩模共享的第一部分被输入到屏蔽门逻辑的第一部分中，并且掩蔽的数据值和掩模共享的第二部分被输入到被掩蔽的门逻辑的第二部分。 识别来自屏蔽门逻辑的第一部分的第一输出和来自屏蔽门逻辑的第二部分的第二输出，其中第一输出或第二输出都是零值。

    Buffer access for side-channel attack resistance
    8.
    发明授权
    Buffer access for side-channel attack resistance 有权

    公开(公告)号：US10747907B2

    公开(公告)日：2020-08-18

    申请号：US14955269

    申请日：2015-12-01

    Applicant: Cryptography Research, Inc

    Inventor： Andrew John Leiserson ,  Mark Evan Marson

    IPC: H04L29/06 ,  G06F21/75 ,  G06F21/78 ,  H04L9/00 ,  G09C1/00 ,  H04L9/06

    Abstract: A cryptographic accelerator (processor) retrieves data blocks for processing from a memory. These data blocks arrive and are stored in an input buffer in the order they were stored in memory (or other known order)—typically sequentially according to memory address (i.e., in-order.) The processor waits until a certain number of data blocks are available in the input buffer and then randomly selects blocks from the input buffer for processing. This randomizes the processing order of the data blocks. The processing order of data blocks may be randomized within sets of data blocks associated with a single read transaction, or across sets of data blocks associated with multiple read transactions.

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