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1.发明授权公开(公告)号：US12013751B2
公开(公告)日：2024-06-18
申请号：US16972560
申请日：2019-06-05
CPC分类号： G06F11/10 , H04L9/0866 , H04L9/3278
摘要： A value corresponding to a physical variation of a device may be received. Furthermore, helper data associated with the physical variation of the device may be received. A result data may be generated based on a combination of the value corresponding to the physical variation of the device and the helper data. An error correction operation may be performed on the result data to identify one or more code words associated with the error correction operation. Subsequently, a target data may be generated based on the one or more code words.
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公开(公告)号：US11861374B2
公开(公告)日：2024-01-02
申请号：US18063984
申请日：2022-12-09
发明人： Ashish Raj , Joel Wittenauer , Winthrop John Wu , Qinglai Xiao , Samatha Gummalla , Bryan Jason Wang
IPC分类号： G06F9/445
CPC分类号： G06F9/445
摘要： A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine. The host device generates a command table for batch processing of a set of address tables that each describe a set of data blocks of a file to be encrypted or decrypted. The DMA engine facilitates a DMA transfer of the command table from the host memory to an RoT memory of the RoT device. The RoT device then performs batch processing of the address tables referenced in the command table. For each address table, the DMA engine copies a set of data blocks from the host memory to the RoT memory, a cryptographic engine encrypts or decrypts the data blocks, and the DMA engine copies the transformed data blocks back to the host memory.
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公开(公告)号：US20230161877A1
公开(公告)日：2023-05-25
申请号：US17992221
申请日：2022-11-22
IPC分类号： G06F21/55
CPC分类号： G06F21/554 , G06F2221/034
摘要： Disclosed systems and techniques are directed to efficient integrity monitoring of computational operations using multiple memory arrays collectively representative of known events associated with the computational operations. Disclosed techniques include obtaining event identification value representative of a state of the computing device associated with execution of an operation on the computing device, obtaining memory pointers and selecting, based on the memory pointers, mapping values from multiple memory arrays, computing an event response value, and classifying the operation among a plurality of classes, based on the event response value.
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4.发明公开公开(公告)号：US20240345916A1
公开(公告)日：2024-10-17
申请号：US18644084
申请日：2024-04-23
CPC分类号： G06F11/10 , H04L9/0866 , H04L9/3278
摘要： A value corresponding to a physical variation of a device may be received. Furthermore, helper data associated with the physical variation of the device may be received. A result data may be generated based on a combination of the value corresponding to the physical variation of the device and the helper data. An error correction operation may be performed on the result data to identify one or more code words associated with the error correction operation. Subsequently, a target data may be generated based on the one or more code words.
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公开(公告)号：US20240176897A1
公开(公告)日：2024-05-30
申请号：US18516605
申请日：2023-11-21
发明人： Winthrop John Wu
CPC分类号： G06F21/602 , G06F21/72 , H04L9/14
摘要： Technologies for protecting a secure context in a hardware root of trust (ROT) are described. One hardware ROT includes key generation logic and a cryptographic circuit. The key generation logic generates a first key from a value, corresponding to a physical variation of the hardware ROT, and first helper data associated with the physical variation of the hardware ROT. The key generation logic generates a second key from the value and second helper data associated with the physical variation of the hardware ROT. The cryptographic circuit receives a first encrypted secure context from off-chip storage and decrypts the first encrypted secure context using the first key to obtain a secure context. The cryptographic circuit encrypts the secure context using the second key to obtain a second encrypted secure context and stores the second encrypted secure context in the off-chip storage.
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公开(公告)号：US20230185745A1
公开(公告)日：2023-06-15
申请号：US18063959
申请日：2022-12-09
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA system includes two or more DMA engines that facilitate transfers of data through a shared memory. The DMA engines may operate independently of each other and with different throughputs. A data flow control module controls data flow through the shared memory by tracking status information of data blocks in the shared memory. The data flow control module updates the status information in response to read and write operations to indicate whether each block includes valid data that has not yet been read or if the block has been read and is available for writing. The data flow control module shares the status information with the DMA engines via a side-channel interface to enable the DMA engines to determine which block to write to or read from.
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公开(公告)号：US20240211171A1
公开(公告)日：2024-06-27
申请号：US18531350
申请日：2023-12-06
IPC分类号： G06F3/06
CPC分类号： G06F3/0658 , G06F3/0619 , G06F3/0679
摘要： A request to perform a memory operation addressed to a first address corresponding to a first logical unit of logical units of a memory is received. Address mask data that corresponds to the logical units is identified. Multiple transformed addresses are determined using the first address and the address mask data. The transformed addresses can include a target address corresponding to the first logical unit and additional addresses corresponding to other logical units. The memory operation is performed at the target address corresponding to the first logical unit and dummy memory operations are performed at the additional addresses corresponding to the additional logical units.
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公开(公告)号：US20230195477A1
公开(公告)日：2023-06-22
申请号：US18063984
申请日：2022-12-09
发明人： Ashish Raj , Joel Wittenauer , Winthrop John Wu , Qinglai Xiao , Samatha Gummalla , Bryan Jason Wang
IPC分类号： G06F9/445
CPC分类号： G06F9/445
摘要： A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine. The host device generates a command table for batch processing of a set of address tables that each describe a set of data blocks of a file to be encrypted or decrypted. The DMA engine facilitates a DMA transfer of the command table from the host memory to an RoT memory of the RoT device. The RoT device then performs batch processing of the address tables referenced in the command table. For each address table, the DMA engine copies a set of data blocks from the host memory to the RoT memory, a cryptographic engine encrypts or decrypts the data blocks, and the DMA engine copies the transformed data blocks back to the host memory.
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9.发明申请公开(公告)号：US20230093306A1
公开(公告)日：2023-03-23
申请号：US17948017
申请日：2022-09-19
IPC分类号： H04L9/06
摘要： Aspects of the present disclosure involve a method and a system to perform the method to obtain a cryptographic output of a plurality of rounds of a cipher, by performing a plurality of modified rounds of the cipher, each of the modified rounds computing an unmasking transform, an operation of a respective round of the cipher, and a masking transform, the unmasking transform being an inverse of the masking transform of a previous round of the cipher.
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10.发明申请公开(公告)号：US20210271542A1
公开(公告)日：2021-09-02
申请号：US16972560
申请日：2019-06-05
摘要： A value corresponding to a physical variation of a device may be received. Furthermore, helper data associated with the physical variation of the device may be received. A result data may be generated based on a combination of the value corresponding to the physical variation of the device and the helper data. An error correction operation may be performed on the result data to identify one or more code words associated with the error correction operation. Subsequently, a target data may be generated based on the one or more code words.
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