公开(公告)号：US09766686B2

公开(公告)日：2017-09-19

申请号：US14154987

申请日：2014-01-14

Applicant: Cisco Technology, Inc.

Inventor： Yi Wang ,  Ruikai Zhang ,  Yongfeng Liu ,  Zhou Yu

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/324 ,  Y02D10/126

Abstract: The embodiments disclosed herein provide a computing device that includes an upstream buffer and downstream data processing circuit that establish a data processing path where the data stored by upstream buffer is received and processed by the downstream data processing circuit. Using a buffer utilization characteristic of the upstream buffer such as its current availability (e.g., the buffer is 50% full) or an input data rate, the computing device adjusts the clock signal used to drive the downstream data processing circuit. For example, if the utilization of the upstream buffer is low, the number of clock edges in the clock signal may be reduced thereby reducing power consumption of the computing device. However, as the utilization of the buffer begins to increase, the computing device may increase the number of clock edges to prevent a buffer overflow.