公开(公告)号：US20220182064A1

公开(公告)日：2022-06-09

申请号：US17115570

申请日：2020-12-08

Applicant: Cisco Technology, Inc.

Inventor： Yongxin LI ,  Romesh Kumar NANDWANA ,  Kadaba LAKSHMIKUMAR

IPC: H03M1/06 ,  H03L7/197 ,  H03L7/081

Abstract: An apparatus includes a first digital-to-time converter (DTC) and a second DTC. The first DTC includes a sequence of delay stages. Each of the delay stages adds a delay to an input signal based on a control signal. Each delay stage includes a comparator and a capacitor coupled to an input of the comparator and to ground. The second DTC is coupled in parallel to the first DTC. The second DTC adds a delay to the input signal based on a complement of the control signal.