公开(公告)号：US12107556B2

公开(公告)日：2024-10-01

申请号：US17448822

申请日：2021-09-24

Applicant: Cisco Technology, Inc.

Inventor： Sanjay Sunder ,  Alexander C. Kurylak ,  Kadaba Lakshmikumar

IPC: H03F3/45 ,  H03G3/30

CPC classification number: H03F3/45475 ,  H03G3/30 ,  H03G2201/103

Abstract: An integrated circuit includes a transimpedance amplifier and an injection circuit. The injection circuit generates a first electrical test signal and injects the first electrical test signal into the transimpedance amplifier. The first electrical test signal or an output of the transimpedance amplifier generated based on the first electrical test signal is used to determine whether the integrated circuit is faulty.

公开(公告)号：US12095421B2

公开(公告)日：2024-09-17

申请号：US17810792

申请日：2022-07-05

Applicant: Cisco Technology, Inc.

Inventor： Craig S. Appel ,  Peter C. Metz ,  Joseph V. Pampanin ,  Sanjay Sunder

IPC: H03F1/02 ,  H03F3/45 ,  H03K5/24

CPC classification number: H03F1/0211 ,  H03F3/45179 ,  H03F3/45663 ,  H03K5/2481

Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.

公开(公告)号：US11639955B2

公开(公告)日：2023-05-02

申请号：US17445616

申请日：2021-08-23

Applicant: Cisco Technology, Inc.

Inventor： Sanjay Sunder ,  Prajwal M. Kasturi ,  Joseph V. Pampanin ,  Craig S. Appel

IPC: G01R31/28

Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.

公开(公告)号：US11411538B2

公开(公告)日：2022-08-09

申请号：US16417295

申请日：2019-05-20

Applicant: Cisco Technology, Inc.

Inventor： Craig S. Appel ,  Peter C. Metz ,  Joseph V. Pampanin ,  Sanjay Sunder

IPC: H03F1/02 ,  H03F3/45 ,  H03K5/24

Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.

公开(公告)号：US10965377B1

公开(公告)日：2021-03-30

申请号：US16745257

申请日：2020-01-16

Applicant: Cisco Technology, Inc.

Inventor： Craig S. Appel ,  Romesh Kumar Nandwana ,  Sanjay Sunder ,  Kadaba Lakshmikumar

IPC: H04B10/00 ,  H04B10/556 ,  G02B6/12 ,  G01B9/02 ,  H04B10/50 ,  H04B10/588 ,  H04B10/25 ,  H04J14/00

Abstract: Thermal tuning and quadrature control of opto-electronic devices using active extinction ratio tracking is proved by phase shifting, via a first phase shifter, a first optical signal carried on a first arm of an interferometer relative to a second optical signal carried on a second arm of the interferometer; combining the first optical signal with the second optical signal as an output signal; detecting a peak value in the output signal; and adjusting a relative phase offset imparted by the first phase shifter on the first optical signal relative to the second optical signal, based on the peak value, to increase an amplitude of the peak value. In various embodiments, the peak value is increased over time to maximize an extinction ratio of the optoelectronic device and maintain the extinction ratio in a maximized state during operation.

公开(公告)号：US12007432B2

公开(公告)日：2024-06-11

申请号：US17813203

申请日：2022-07-18

Applicant: Cisco Technology, Inc.

Inventor： Sanjay Sunder ,  Alexander C. Kurylak

IPC: G01R31/28

CPC classification number: G01R31/2853 ,  G01R31/2856

Abstract: Techniques for testing connectivity between a first integrated circuit (IC) and a second IC of an electronics package are described. An example technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode of the second IC to forward biased. A connectivity test between the first and second ICs is performed, when the photodiode is forward biased. Another technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode in the second IC to reverse biased. A first voltage is measured at an input of a transimpedance amplifier (TIA) in the first IC when the photodiode is reverse biased. The switch(es) are controlled to change the bias direction of the photodiode to forward biased. A second voltage is measured at the input of the TIA when the photodiode is forward biased.

公开(公告)号：US11099229B2

公开(公告)日：2021-08-24

申请号：US16740296

申请日：2020-01-10

Applicant: Cisco Technology, Inc.

Inventor： Sanjay Sunder ,  Prajwal M. Kasturi ,  Joseph V. Pampanin ,  Craig S. Appel

IPC: G01R31/28

Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.

公开(公告)号：US20210215754A1

公开(公告)日：2021-07-15

申请号：US16740296

申请日：2020-01-10

Applicant: Cisco Technology, Inc.

Inventor： Sanjay Sunder ,  Prajwal M. Kasturi ,  Joseph V. Pampanin ,  Craig S. Appel

IPC: G01R31/28

Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.