METHODS AND SYSTEMS FOR ENSURING PROGRAM CODE FLOW INTEGRITY

    公开(公告)号:US20190073472A1

    公开(公告)日:2019-03-07

    申请号:US15694881

    申请日:2017-09-04

    Abstract: In one embodiment a device is described, the device including a memory operative to store an program, a storage operative to store a reference check value for at least one operation in the program, a processor operative to execute the program, including, determining a run-time check value upon execution of the at least one operation in the program, comparing the stored reference check value with the run-time check value, storing the run-time check value as a pre-branch run-time check value prior to entering a conditional branch of the program when the compared stored reference check value and the run-time check value are equal values, resetting the run-time check value of the executing program to the pre-branch run-time check value upon exiting the conditional branch of the program, wherein the reference check value, the run-time check value, and the pre-branch run-time check value are determined as a result of a single function. Related apparatus, methods and systems are also described.

    Timing based camouflage circuit
    2.
    发明授权

    公开(公告)号:US10262956B2

    公开(公告)日:2019-04-16

    申请号:US15640615

    申请日:2017-07-03

    Abstract: In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.

    Timing based camouflage circuit
    3.
    发明授权

    公开(公告)号:US10396043B2

    公开(公告)日:2019-08-27

    申请号:US16285598

    申请日:2019-02-26

    Abstract: In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.

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