公开(公告)号：US20150188407A1

公开(公告)日：2015-07-02

申请号：US14143150

申请日：2013-12-30

申请人： Cambridge Silicon Radio Limited

发明人： Barnaby Golder ,  Peter Andrew Rees Williams ,  Sukanta Kishore Panigrahi ,  Timothy Charles Clapp ,  Richard Andrew Wilkinson

IPC分类号： H02M1/088 ,  H02J1/00 ,  H02M3/158

CPC分类号： H02M1/088 ,  H02J1/00 ,  H02M3/158 ,  H02M3/1582 ,  H02M2001/0003 ,  H02M2001/009 ,  Y10T307/406

摘要： A method of operating a voltage regulator including a source voltage rail and a plurality of output voltage rails, the method including: converting a source voltage on the source voltage rail to a respective output voltage on each output voltage rail; selecting an output voltage rail; comparing the output voltage on the selected output voltage rail to a reference voltage for the selected output voltage rail; and if the output voltage of the selected output voltage rail is less than the reference voltage for the selected output voltage rail, controlling the voltage regulator to increase the output voltage on the selected output voltage rail, wherein the frequency at which an output voltage rail is selected is dependent upon the rate at which the voltage regulator has previously increased the output voltage on that output voltage rail.

摘要翻译： 一种操作包括源极电压轨道和多个输出电压轨道的电压调节器的方法，所述方法包括：将源极电压轨上的源极电压转换为每个输出电压轨上的相应输出电压; 选择输出电压轨; 将所选输出电压轨上的输出电压与所选输出电压轨的参考电压进行比较; 并且如果所选择的输出电压轨的输出电压小于所选择的输出电压轨的参考电压，则控制电压调节器增加所选输出电压轨上的输出电压，其中输出电压轨为 选择取决于电压调节器先前增加该输出电压轨上的输出电压的速率。

公开(公告)号：US20150185263A1

公开(公告)日：2015-07-02

申请号：US14141021

申请日：2013-12-26

申请人： Cambridge Silicon Radio Limited

发明人： Timothy Charles Clapp ,  Duncan Angus McLeod ,  Michael John Story

IPC分类号： G01R23/02 ,  H03L7/085 ,  H03L7/099

CPC分类号： G01R23/02 ,  H03K23/54 ,  H03L7/085 ,  H03L7/091 ,  H03L7/099 ,  H03L7/18

摘要： A frequency locked loop for generating a clock signal, comprising: a controllable oscillator configured to, in dependence on a control signal, generate an oscillator signal having an oscillator signal frequency; a frequency divider coupled to the controllable oscillator configured to reduce the oscillator signal frequency to form a divided oscillator signal frequency; and a frequency detector coupled to the frequency divider and configured to generate the control signal in dependence on a reference signal frequency; wherein the frequency divider comprises a first counter and a second counter, the first counter configured to be clocked by the oscillator signal and to produce a first counter output signal, and the second counter configured to be clocked by the first counter output signal.

摘要翻译： 一种用于产生时钟信号的锁频环路，包括：可控振荡器，被配置为根据控制信号产生具有振荡器信号频率的振荡器信号; 耦合到所述可控振荡器的分频器，被配置为减小所述振荡器信号频率以形成分频振荡器信号频率; 以及频率检测器，耦合到所述分频器并且被配置为根据参考信号频率产生所述控制信号; 其中所述分频器包括第一计数器和第二计数器，所述第一计数器配置为由所述振荡器信号计时并产生第一计数器输出信号，所述第二计数器被配置为由所述第一计数器输出信号计时。