公开(公告)号：US10534887B1

公开(公告)日：2020-01-14

申请号：US15994255

申请日：2018-05-31

申请人： Cadence Design Systems, Inc.

发明人： Sravasti Nair ,  Subhashis Mandal ,  Chandra Prakash Manglani ,  Nikhil Garg ,  Preeti Kapoor ,  Kanaka Raju Gorle

IPC分类号： G06F17/50

摘要： A method including creating a plurality of component groups in a circuit layout coupling multiple components in each component group of the plurality of component groups with a power rail, a ground rail, or a bulk, is provided. The method includes creating internal clusters based on a group cost and including the group cost in an overall cost function, forming a gap between two component groups of the plurality of component groups, and filling the gap with a first gap cell adjacent to a first power rail and to a first ground rail, and a second gap cell adjacent to the first gap cell. A system and a non-transitory, machine readable medium storing instructions to perform the above method are also provided.

公开(公告)号：US10452807B1

公开(公告)日：2019-10-22

申请号：US15476921

申请日：2017-03-31

申请人： Cadence Design Systems, Inc.

发明人： Karun Sharma ,  Nikhil Garg ,  Juno Jui-Chuan Lin ,  Subhashis Mandal ,  Chandra Prakash Manglani ,  Kanaka Raju Gorle ,  Henry Yu

IPC分类号： G06F17/50

摘要： Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.

公开(公告)号：US10984164B1

公开(公告)日：2021-04-20

申请号：US16661974

申请日：2019-10-23

申请人： Cadence Design Systems, Inc.

发明人： Ankur Chaplot ,  Yashu Gupta ,  Nikhil Garg ,  Sachin Shrivastava ,  Michaela Guiney ,  Sankalp Srivastava

IPC分类号： G06F30/392 ,  G06F30/327 ,  G06F30/398 ,  G06F111/04

摘要： An approach is described for a method, system, and product, the approaching includes identification of an integrated circuit design, identification of sync groups (nets having synchronous voltage levels), generation of a physical design having sync group constraints, and performance of design rule checking on a physical design based on at least transferred sync group information. This provides for performing design rule analysis at least using small minimum spacing requirements then would otherwise be required with prior techniques. In some embodiments, the approach includes a verification process that ensures that synchronous voltage behavior is appropriately associated with members of respective sync groups and cleans up old association data that is no longer relevant/correct.