专利检索 ap:("Cadence Design Systems, Inc.") AND inv:"Anubhav Srivastava" 第 1 页

1.

发明授权
System, method, and computer program product for computing formal coverage data compatible with dynamic verification 有权

公开(公告)号：US10515169B1

公开(公告)日：2019-12-24

申请号：US15863917

申请日：2018-01-06

申请人： Cadence Design Systems, Inc.

发明人： David Ryan Spatafore , Amit Verma , Anubhav Srivastava

IPC分类号： G06F17/50

摘要： The present disclosure is directed towards electronic circuit design and verification. Embodiments may include receiving, using a processor, source code corresponding to at least a portion of an electronic design and generating at least one coverage model for each of a dynamic verification and a formal verification. The method may further include determining a formal data set including stimuli coverage status, cone of influence coverage status, and proof coverage status and consolidating the formal data set using a user-programmable consolidation function to generate a combined formal coverage data set.