Scalable low-latency mesh interconnect for switch chips

    公开(公告)号:US10102168B2

    公开(公告)日:2018-10-16

    申请号:US15063387

    申请日:2016-03-07

    Abstract: A device implementing a scalable low-latency mesh may include a memory management unit, an egress processor, and an egress cell circuit that includes at least a first queue and a second queue. The memory management unit may be configured to buffer first cells for transmission. The egress cell circuit may be configured to queue the first cells from the memory management unit in the first queue, queue second cells from an off-chip memory management unit of another device in the second queue, and schedule the first cells from the first queue and second cells from the second queue for transmission via an egress processor. The egress processor may be configured to transmit the first and second cells over at least one first port.

    Flexible flow table with programmable state machine

    公开(公告)号:US10164796B2

    公开(公告)日:2018-12-25

    申请号:US15155137

    申请日:2016-05-16

    Abstract: A network switch for network communications includes an embedded programmable state machine to monitor data flows through the switch. The programmable state machine is configured to retain selectable states of selectable data packet fields. Programmable switch logic operative with the programmable state machine is configured to output one or more potential actions to be taken based on a selectable computation of detected selectable states. The programmable state machine can be implemented with either table lookups or flexible logic.

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