公开(公告)号：US20170228335A1

公开(公告)日：2017-08-10

申请号：US15063387

申请日：2016-03-07

Applicant: BROADCOM CORPORATION

Inventor： Surendra ANUBOLU ,  Mohan Venkatachar KALKUNTE

IPC: G06F13/40 ,  G06F13/42 ,  G06F9/48

CPC classification number: G06F13/4022 ,  G06F9/4881 ,  G06F13/4282

Abstract: A device implementing a scalable low-latency mesh may include a memory management unit, an egress processor, and an egress cell circuit that includes at least a first queue and a second queue. The memory management unit may be configured to buffer first cells for transmission. The egress cell circuit may be configured to queue the first cells from the memory management unit in the first queue, queue second cells from an off-chip memory management unit of another device in the second queue, and schedule the first cells from the first queue and second cells from the second queue for transmission via an egress processor. The egress processor may be configured to transmit the first and second cells over at least one first port.