公开(公告)号：US09455915B2

公开(公告)日：2016-09-27

申请号：US14139185

申请日：2013-12-23

Applicant: Broadcom Corporation

Inventor： Santanu Sinha ,  Karen Schramm

IPC: H04L12/801 ,  H04L12/825 ,  H04L12/863 ,  H04L12/815 ,  H04L12/891

CPC classification number: H04L47/12 ,  H04L47/22 ,  H04L47/25 ,  H04L47/41 ,  H04L47/50

Abstract: Hierarchical congestion identification and control hardware supports multi-level congestion control at flow, tenant and virtual machine (VM) levels. Hardware implementation expedites response to congestion notifications and frees-up processor bandwidth. A hierarchy of transmit shapers in a transmit ring scheduler isolate rate adjustments for flows, tenants and VMs. The hierarchy of shapers provide a hierarchy of congestion control nodes to control flows and aggregate flows. Hardware quickly associates congested flows with shapers before or after receiving a congestion notification. The associations may be used by any flow control algorithm to selectively rate-control shapers to control flow rates. Shaper associations and configured states, scheduler configuration, congestion states, thresholds and other flow information may be stored and monitored to filter data flows that need attention and to raise alerts at flow, tenant and VM levels. Congestion control occurs fast and without packet modification, queue or ring switching or queue accumulation.

Abstract translation: 分层拥塞识别和控制硬件支持流，租户和虚拟机（VM）级别的多级拥塞控制。 硬件实现加速了对拥塞通知的响应和释放处理器带宽。 发射环调度器中的发送成形器的层次结构隔离流量，租户和虚拟机的速率调整。 整形器的层次结构提供了拥塞控制节点的层次结构，以控制流和聚合流。 在收到拥塞通知之前或之后，硬件会使拥挤的流量与挤压器相关联。 这些关联可以被任何流量控制算法用于选择性地对整形器进行速率控制以控制流量。 可以存储和监视整形器关联和配置状态，调度器配置，拥塞状态，阈值和其他流信息以过滤需要关注的数据流并且以流，租户和VM级别来提高警报。 拥塞控制发生得很快，没有包修改，队列或环路切换或队列累积。

公开(公告)号：US20150172193A1

公开(公告)日：2015-06-18

申请号：US14139185

申请日：2013-12-23

Applicant: Broadcom Corporation

Inventor： Santanu Sinha ,  Karen Schramm

IPC: H04L12/801 ,  H04L12/863 ,  H04L12/825

CPC classification number: H04L47/12 ,  H04L47/22 ,  H04L47/25 ,  H04L47/41 ,  H04L47/50

Abstract: Hierarchical congestion identification and control hardware supports multi-level congestion control at flow, tenant and virtual machine (VM) levels. Hardware implementation expedites response to congestion notifications and frees-up processor bandwidth. A hierarchy of transmit shapers in a transmit ring scheduler isolate rate adjustments for flows, tenants and VMs. The hierarchy of shapers provide a hierarchy of congestion control nodes to control flows and aggregate flows. Hardware quickly associates congested flows with shapers before or after receiving a congestion notification. The associations may be used by any flow control algorithm to selectively rate-control shapers to control flow rates. Shaper associations and configured states, scheduler configuration, congestion states, thresholds and other flow information may be stored and monitored to filter data flows that need attention and to raise alerts at flow, tenant and VM levels. Congestion control occurs fast and without packet modification, queue or ring switching or queue accumulation.

Abstract translation: 分层拥塞识别和控制硬件支持流，租户和虚拟机（VM）级别的多级拥塞控制。 硬件实现加速了对拥塞通知的响应和释放处理器带宽。 发射环调度器中的发送成形器的层次结构隔离流量，租户和虚拟机的速率调整。 整形器的层次结构提供了拥塞控制节点的层次结构，以控制流和聚合流。 在收到拥塞通知之前或之后，硬件会使拥挤的流量与挤压器相关联。 这些关联可以被任何流量控制算法用于选择性地对整形器进行速率控制以控制流量。 可以存储和监视整形器关联和配置状态，调度器配置，拥塞状态，阈值和其他流信息以过滤需要关注的数据流并且以流，租户和VM级别来提高警报。 拥塞控制发生得很快，没有包修改，队列或环路切换或队列累积。

公开(公告)号：US10027590B2

公开(公告)日：2018-07-17

申请号：US14628173

申请日：2015-02-20

Applicant: BROADCOM CORPORATION

Inventor： Santanu Sinha ,  Mohan Venkatachar Kalkunte

IPC: H04L12/801 ,  H04L12/931 ,  H04L12/935 ,  H04L12/803 ,  H04L12/841

Abstract: A network device implementing the subject system for end to end flow control may include at least one processor circuit that may be configured to detect that congestion is being experienced by at least one queue of a port and identify another network device that is transmitting downstream traffic being queued at the at least one queue of the port that is at least partially causing the congestion. The at least one processor circuit may be further configured to generate an end to end flow control message that comprises an identifier of the port, the end to end flow control message indicating that the downstream traffic should be flow controlled at the another network device. The at least one processor circuit may be further configured to transmit, out-of-band and through at least one intermediary network device, the end to end flow control message to the another network device.