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公开(公告)号：US20250151583A1
公开(公告)日：2025-05-08
申请号：US19014454
申请日：2025-01-09
Inventor： Pan Xu , Zhidong Yuan , Yongqian Li , Can Yuan
IPC: H10K59/80 , H10K59/12 , H10K59/124
Abstract: Provided are a display panel and a method for manufacturing the same, and a display device. The display panel includes: a base substrate including a display area and a peripheral area; a separator located at the peripheral area and including at least one separation portion, each separation portion including a first and a second separation layer, and the orthographic projection of the first separation layer on the base substrate is within that of the second separation layer; a cathode including: a first cathode portion, and a second cathode spaced apart from the first cathode portion; and an encapsulation layer including a first and a second inorganic layer, and an organic layer located between the first and the second inorganic layer, wherein edges of the orthographic projections of the first inorganic layer, the organic layer, and the second inorganic layer on the base substrate overlap.
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公开(公告)号：US11955089B2
公开(公告)日：2024-04-09
申请号：US17680956
申请日：2022-02-25
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan , Pan Xu
IPC: G09G3/3275 , H10K59/131
CPC classification number: G09G3/3275 , H10K59/131 , G09G2310/061
Abstract: Provided is a display substrate. The display substrate includes two pixels arranged along a first direction and adjacent to each other on a base substrate, and a pixel circuit in each of the two pixels includes a drive transistor, a first reset transistor, and a second reset transistor. A display device is also provided.
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公开(公告)号：US11929022B2
公开(公告)日：2024-03-12
申请号：US17641991
申请日：2021-05-18
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan
IPC: G09G3/3225
CPC classification number: G09G3/3225 , G09G2310/0297 , G09G2310/08
Abstract: The present disclosure provides a multiplexing circuitry, a multiplexing method, a multiplexing module, and a display device. The multiplexing circuitry includes N multiplexing unit circuitries, N energy storage unit circuitries and N control unit circuitries. An nth multiplexing unit circuitry is configured to enable an nth output data line to be electrically coupled to or electrically decoupled from an input data line under the control of a potential at an nth control end; an nth energy storage unit circuitry is configured to control a potential at the nth control end in accordance with an nth clock signal; and an nth control unit circuitry is configured to enable the nth control end to be electrically coupled to or electrically decoupled from an nth switch control line in accordance with a control voltage signal and an nth switch control signal.
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公开(公告)号：US11910680B2
公开(公告)日：2024-02-20
申请号：US16976839
申请日：2019-11-29
Inventor： Can Yuan , Yongqian Li , Meng Li , Zhidong Yuan , Dacheng Zhang , Lang Liu
IPC: H01L27/32 , H10K59/131 , G09G3/3233 , G09G3/3266 , G09G3/3275 , H10K50/813 , H10K50/824 , H10K59/122 , H10K59/124 , H10K59/121 , H10K71/00
CPC classification number: H10K59/1315 , G09G3/3233 , G09G3/3266 , G09G3/3275 , H10K50/813 , H10K50/824 , H10K59/122 , H10K59/124 , H10K59/1216 , H10K71/00 , G09G2300/0426
Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array in a first direction and a second direction, the first direction intersecting with the second direction. The display substrate further includes data lines extended in the first direction, and the data lines are connected in one-to-one correspondence with the sub-pixels in columns in each row of sub-pixels, so as to provide data signals respectively; the display substrate further includes auxiliary electrode lines extended in the first direction which are configured to be electrically connected with a second electrode of the light emitting element to provide a second power voltage; each of the auxiliary electrode lines is spaced from any one of the plurality of data lines by at least one column of sub-pixels.
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公开(公告)号：US11887683B2
公开(公告)日：2024-01-30
申请号：US17417518
申请日：2020-12-29
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan , Wenchao Bao
IPC: G11C19/28 , G09G3/3266
CPC classification number: G11C19/28 , G09G3/3266 , G09G2310/0286
Abstract: The present disclosure provides a shift register unit, a driving method, a gate driving circuit and a display device. The shift register unit includes a pull-down node control circuit; the pull-down node control circuit is electrically connected to an input terminal, a reset terminal, a first voltage terminal, a second voltage terminal and a pull-down node, respectively, and is configured to, under the control of an input signal provided by the input terminal and a reset signal provided by the reset terminal, control the pull-down node to be electrically conducted to the first voltage terminal or the second voltage terminal, and control to hold a potential of the pull-down node.
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Patent Agency Ranking
公开(公告)号：US11875750B2
公开(公告)日：2024-01-16
申请号：US17635471
申请日：2020-12-26
Inventor： Zhidong Yuan , Pan Xu , Can Yuan , Yongqian Li , Zhongyuan Wu
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
CPC classification number: G09G3/3266 , G09G3/3233 , G11C19/287 , G09G2300/0819 , G09G2300/0852 , G09G2310/0286 , G09G2310/08
Abstract: An array substrate includes: a substrate, at least one gate driving circuit and at least one clock signal line that are located on a same side of the substrate. The gate driving circuit includes a plurality of cascaded shift registers located in different rows, the plurality of shift registers are divided into at least two groups of shift registers, each group of shift registers includes at least one shift register, located in a same column. A gate driving circuit in the at least one gate driving circuit corresponds to at least one clock signal line. The clock signal line includes a main body transmission section configured to transmit a clock signal, and at least two branch transmission sections connected to the main body transmission section. Each branch transmission section is connected to a clock signal input terminal of each shift register in a respective group of shift registers.
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公开(公告)号：US11508295B2
公开(公告)日：2022-11-22
申请号：US17309360
申请日：2020-08-12
Inventor： Zhongyuan Wu , Yongqian Li , Can Yuan , Xuehuan Feng , Zhidong Yuan
IPC: G09G3/3225 , G11C19/28
Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, and a GOA circuit, a source electrode IC and PLG wires arranged on the base substrate, and the PLG wires connect the GOA circuit with the source electrode IC. The GOA circuit transmits a GOA signal, and the GOA signal comprises a cascade signal and a non-cascade signal. The PLG wires comprise a first PLG wire group and at least one second PLG wire group, the first PLG wire group transmits the cascade signal, the second PLG wire group transmits the non-cascade signal, a line width of the first PLG wire group is smaller than that of the second PLG wire group, and the first PLG wire group is located at a side of the second PLG wire group distal to an active area of the base substrate.
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公开(公告)号：US11482688B2
公开(公告)日：2022-10-25
申请号：US16762985
申请日：2019-07-05
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan
Abstract: A display substrate including a plurality of light emitting elements respectively in a plurality of subpixels configured to emit light for image display is provided. A respective one of the plurality of subpixels includes a base substrate; a first auxiliary cathode; a passivation layer; a first insulating layer; a second auxiliary cathode; a second insulating layer; and a pixel definition layer. The display substrate has a cathode aperture extending through the pixel definition layer and an auxiliary cathode aperture extending through the first insulating layer and the passivation layer. A cathode of a respective one of the plurality of light emitting elements extends into the cathode aperture to electrically connect with the second auxiliary cathode. The second auxiliary cathode extends into the auxiliary cathode aperture to electrically connect with the first auxiliary cathode.
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9.发明授权公开(公告)号：US11250784B2
公开(公告)日：2022-02-15
申请号：US16642469
申请日：2019-07-29
Inventor： Zhidong Yuan , Yongqian Li , Meng Li , Can Yuan
IPC: G09G3/3266 , G11C19/28
Abstract: The present disclosure discloses a shift register, a driving method thereof, a gate drive circuit, an array substrate and a display device. With a signal control circuit, a branch control circuit, a cascade signal output circuit and at least two scan signal output circuits, each shift register can output at least two scan signals to correspond to different gate lines in a display panel. This can reduce the number of shift registers in a gate drive circuit and the space occupied by the gate drive circuit and can achieve an ultra-narrow frame design, as compared with an existing shift register that can only output one scan signal. Moreover, as signals of different output control node do not influence each other, the output stability can also be improved.
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10.发明申请公开(公告)号：US20210408160A1
公开(公告)日：2021-12-30
申请号：US16963346
申请日：2019-09-27
Inventor： Can Yuan , Yongqian Li , Pan Xu , Zhidong Yuan , Meng Li , Xuehuan Feng , Zehua Ding
IPC: H01L27/32 , G09G3/3225
Abstract: An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.
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