公开(公告)号：US11483010B2

公开(公告)日：2022-10-25

申请号：US17095606

申请日：2020-11-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Junrui Zhang ,  Xuehui Zhu ,  Ronghua Lan ,  Xin Xiang ,  Xiaoqiao Liu ,  Xizhu Peng ,  He Tang

IPC: H03M9/00

Abstract: An output control circuit, a method for transmitting data, and an electronic device are disclosed. The output control circuit includes: a serial-to-parallel conversion circuit configured to obtain at least one group of parallel data through a serial-to-parallel conversion; an intermediate-stage cache circuit configured to divide the at least one group of parallel data into at least two categories of subgroup parallel data according to sequence of serial-to-parallel conversion; a latch output circuit including a plurality of latch arrays each of which receiving any category of subgroup parallel data and latching and outputting any subgroup parallel data in any category of subgroup parallel data; and a selection control circuit configured to, within an effective pulse duration of the any subgroup parallel data, control a latch array for the any subgroup parallel data in the plurality of latch arrays to latch and output the any subgroup parallel data.

公开(公告)号：US20210152184A1

公开(公告)日：2021-05-20

申请号：US17095606

申请日：2020-11-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Junrui Zhang ,  Xuehui Zhu ,  Ronghua Lan ,  Xin Xiang ,  Xiaoqiao Liu ,  Xizhu Peng ,  He Tang

IPC: H03M9/00

Abstract: An output control circuit, a method for transmitting data, and an electronic device are disclosed. The output control circuit includes: a serial-to-parallel conversion circuit configured to obtain at least one group of parallel data through a serial-to-parallel conversion; an intermediate-stage cache circuit configured to divide the at least one group of parallel data into at least two categories of subgroup parallel data according to sequence of serial-to-parallel conversion; a latch output circuit including a plurality of latch arrays each of which receiving any category of subgroup parallel data and latching and outputting any subgroup parallel data in any category of subgroup parallel data; and a selection control circuit configured to, within an effective pulse duration of the any subgroup parallel data, control a latch array for the any subgroup parallel data in the plurality of latch arrays to latch and output the any subgroup parallel data.