公开(公告)号：US3555184A

公开(公告)日：1971-01-12

申请号：US3555184D

申请日：1964-10-21

Applicant: BELL TELEPHONE LABOR INC

Inventor： TOWNLEY RAY C

IPC: G11C21/02 ,  H04L13/08 ,  H04L5/24

CPC classification number: G11C21/026 ,  H04L13/08

Abstract: Incoming serial data from a plurality of lines dedicated to different signaling rates is arranged in parallel form by an assembler which scans the lines and applies the interleaved bits to parallel gate circuits. The gate circuits are enabled to pass the bits to delay line stores by a logic circuit which detects incoming character start elements and thereafter successively operates the gates when the active lines are sampled at the theoretical midpoint of each successive code element. The stores are then simultaneously read out to pass the elements of each data character, in parallel, to a register.

公开(公告)号：US3401235A

公开(公告)日：1968-09-10

申请号：US42176264

申请日：1964-12-29

Applicant: BELL TELEPHONE LABOR INC

Inventor： CORBIN JOSEPH E ,  HELFRICH JOHN H ,  HELLER KENNETH A ,  NICODEMUS KEITH L ,  SMITH JR GEORGE W ,  SPENCER JR ALBERT E ,  TOWNLEY RAY C

IPC: H04J3/00 ,  H04J3/14 ,  H04L5/22 ,  H04Q11/04

CPC classification number: H04Q11/04 ,  H04J3/00 ,  H04J3/14 ,  H04L5/22 ,  H04Q11/0407