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    Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign
    4.
    发明授权
    Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign 有权

    公开(公告)号：US07523436B2

    公开(公告)日：2009-04-21

    申请号：US11385767

    申请日：2006-03-22

    申请人： Masaharu Mizuno ,  Naotaka Maeda

    发明人： Masaharu Mizuno ,  Naotaka Maeda

    IPC分类号： G06F17/50

    CPC分类号： H01L27/118

    摘要： An ASIC includes a function layer formed with plural universal logic cells, a common layer formed with conductive strips connected to the universal logic cells and common to other ASICs and a customized layer having at least two metallization layers assigned to conductive strips extending in certain directions parallel to one another and other conductive strips extending in perpendicular directions to the certain directions, respectively, and an inter-layered insulating layer formed with conductive plugs selectively connected between the conductive strips and the other conductive strips, wherein the conductive strips have respective values of length such that the conductive plugs are located on both ends thereof, whereby the conductive strips, other conductive strips and the conductive plugs form plural signal paths reduced in total contact resistance and parasitic capacitance.

    Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign
    5.
    发明授权
    Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign 有权

    公开(公告)号：US07047514B2

    公开(公告)日：2006-05-16

    申请号：US10114038

    申请日：2002-04-03

    申请人： Masaharu Mizuno ,  Naotaka Maeda

    发明人： Masaharu Mizuno ,  Naotaka Maeda

    IPC分类号： G06F17/50

    CPC分类号： H01L27/118

    摘要： An ASIC includes a function layer formed with plural universal logic cells, a common layer formed with conductive strips connected to the universal logic cells and common to other ASICs and a customized layer having at least two metallization layers assigned to conductive strips extending in certain directions parallel to one another and other conductive strips extending in perpendicular directions to the certain directions, respectively, and an inter-layered insulating layer formed with conductive plugs selectively connected between the conductive strips and the other conductive strips, wherein the conductive strips have respective values of length such that the conductive plugs are located on both ends thereof, whereby the conductive strips, other conductive strips and the conductive plugs form plural signal paths reduced in total contact resistance and parasitic capacitance.

    General-purpose logic array and ASIC using the same
    6.
    发明授权
    General-purpose logic array and ASIC using the same 有权

    公开(公告)号：US06992504B2

    公开(公告)日：2006-01-31

    申请号：US10385697

    申请日：2003-03-12

    申请人： Masaharu Mizuno

    发明人： Masaharu Mizuno

    IPC分类号： H30K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17736 ,  H03K19/17796

    摘要： A general-purpose logic cell array includes a plurality of cells and a lower wiring layer. The plurality of cells are formed on a substrate, and each of the plurality of cells includes a plurality of transistors. The lower wiring layer is formed above the plurality of cells, and which connects the plurality of transistors in each of the plurality of cells such that each of the plurality of cells has an elementary logic circuit. Information of the general-purpose logic cell array is provided to a user. The elementary logic circuits may be one of a gate circuit, a selector, an inverter and a flip-flop.

    Semiconductor device having universal logic cell
    7.
    发明申请
    Semiconductor device having universal logic cell 有权
    具有通用逻辑单元的半导体器件

    公开(公告)号：US20050218936A1

    公开(公告)日：2005-10-06

    申请号：US11092943

    申请日：2005-03-30

    申请人： Masaharu Mizuno ,  Kazuhiro Nakajima

    发明人： Masaharu Mizuno ,  Kazuhiro Nakajima

    IPC分类号： H01L21/822 ,  H01L27/04 ,  H03K19/173 ,  H03K19/0175

    CPC分类号： H03K19/173

    摘要： A universal logic module includes: a first inverter outputting an inverted input signal to an output terminal through a first transfer gate, the inverted input signal having an inverted level of an input signal provided from a first input terminal; and a second inverter outputting an inverted logic signal to the output terminal through a second transfer gate, the inverted logic signal having an inverted level of a first logic signal. The first input terminal is connected to one of a power supply line and a ground line. An input of the first transfer gate is directly connected to the other of the power supply line and the ground line. The first and the second transfer gates are complementarily turned on/off according to a level of a second logic signal. A result of a logical operation between the first and the second logic signals is outputted from the output terminal.

    摘要翻译： 通用逻辑模块包括：第一反相器，通过第一传输门将反相输入信号输出到输出端，反相输入信号具有从第一输入端提供的输入信号的反相电平; 以及第二反相器，通过第二传输门将输出反相逻辑信号输出到输出端，反相逻辑信号具有第一逻辑信号的反相电平。 第一输入端子连接到电源线和接地线之一。 第一传输门的输入直接连接到电源线和接地线中的另一个。 根据第二逻辑信号的电平，第一和第二传输门互补地导通/截止。 从输出端子输出第一和第二逻辑信号之间的逻辑运算的结果。

    Universal logic module and ASIC using the same
    8.
    发明授权
    Universal logic module and ASIC using the same 有权
    通用逻辑模块和ASIC使用相同

    公开(公告)号：US06946875B2

    公开(公告)日：2005-09-20

    申请号：US10325572

    申请日：2002-12-19

    申请人： Kenji Yamamoto ,  Masaharu Mizuno ,  Kazuhiro Nakajima

    发明人： Kenji Yamamoto ,  Masaharu Mizuno ,  Kazuhiro Nakajima

    IPC分类号： H01L21/82 ,  H03K19/00 ,  H03K19/173 ,  H03K19/094

    CPC分类号： H03K19/1735

    摘要： A universal logic module that may have a reduced off-leak current in universal logic cells (100) not used as logic circuits has been disclosed. A universal logic module may include universal logic cells (100) that may be formed with a second wiring for connecting universal logic cells (100) from a base configuration formed with a first wiring. Unused universal logic cell (100) may include transistors in basic cells (A to E) that are non-connected to a power supply (VDD) and/or a ground potential (VSS). Furthermore, unused universal logic cell (100) may include transistors in basic cells (A to E) that may provide a capacitor between a power supply (VDD) and a ground potential (VSS). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.

    摘要翻译： 已经公开了可以在不用作逻辑电路的通用逻辑单元（100）中具有减小的漏电流的通用逻辑模块。 通用逻辑模块可以包括可以形成有第二布线的通用逻辑单元（100），用于将通用逻辑单元（100）与形成有第一布线的基座配置相连接。 未使用的通用逻辑单元（100）可以包括未连接到电源（VDD）和/或接地电位（VSS）的基本单元（A至E）中的晶体管。 此外，未使用的通用逻辑单元（100）可以包括可在电源（VDD）和接地电位（VSS）之间提供电容器的基本单元（A至E）中的晶体管。 以这种方式，可以减少泄漏电流，并且可以减少电力线和/或接地线上的噪声。

    Semiconductor integrated circuit and its layout method
    9.
    发明授权
    Semiconductor integrated circuit and its layout method 有权
    半导体集成电路及其布局方法

    公开(公告)号：US06753702B2

    公开(公告)日：2004-06-22

    申请号：US10230197

    申请日：2002-08-29

    申请人： Masaharu Mizuno ,  Shigeki Sakai ,  Naotaka Maeda

    发明人： Masaharu Mizuno ,  Shigeki Sakai ,  Naotaka Maeda

    IPC分类号： H03K1900

    CPC分类号： H03K19/1737 ,  G06F1/06 ,  G06F1/10 ,  G06F17/5068 ,  H03K19/1735

    摘要： The master slice type semiconductor integrated circuit includes sequential circuit cells (2) and combinational circuit cells (3), which are alternately arranged in an inner core area on a semiconductor chip (1), and a plurality of selective driving elements (MC101 to MC108, MC201 to MC216 and MC301 to MC316), which are connected in a shape of a tree, for selectively distributing a poliphase clock signal for each division area formed by uniformly dividing the inner core area. The plurality of selective driving elements are placed and connected on the semiconductor chip such that load and wiring length between the sequential circuit cells within the respective division areas and input terminals to which the poliphase clock signal is inputted are equal. Due to this configuration, it is possible to cope with a poliphase clock, and also possible to reduce a clock skew between circuits, and further possible to provide a master slice type semiconductor integrated circuit in which an electric power consumption can be reduced.

    摘要翻译： 主片式半导体集成电路包括交替布置在半导体芯片（1）上的内核区域中的顺序电路单元（2）和组合电路单元（3），以及多个选择驱动元件（MC101至MC108 ，MC201〜MC216以及MC301〜MC316），其以树形连接，用于选择性地分配由均匀分割内芯区域形成的各分割区域的波形时钟信号。 多个选择性驱动元件被放置并连接在半导体芯片上，使得相应的划分区域内的顺序电路单元和输入有相位时钟信号的输入端之间的负载和布线长度相等。 由于这种结构，可以应付脉冲时钟，也可以减少电路之间的时钟偏移，并且还可以提供能够降低电力消耗的主分片式半导体集成电路。

    Method for designing integrated circuit incorporating memory macro
    10.
    发明申请
    Method for designing integrated circuit incorporating memory macro 有权
    集成电路集成存储器宏的方法

    公开(公告)号：US20090201758A1

    公开(公告)日：2009-08-13

    申请号：US12379041

    申请日：2009-02-11

    申请人： Masaharu Mizuno ,  Masahiro Suzuki ,  Shinichi Uchino

    发明人： Masaharu Mizuno ,  Masahiro Suzuki ,  Shinichi Uchino

    IPC分类号： G11C8/18 ,  G06F17/50

    CPC分类号： G11C8/18 ,  G06F17/505

    摘要： An integrated circuit design method is provided in which memory instances are assigned to memory macros integrated within an integrated circuit. The integrated circuit design method includes: assigning a plurality of memory instances operating at the same operation frequency to a single memory macro; arranging a frequency multiplier which receives a first clock signal to generate a second clock signal through frequency multiplication of the first clock signal, and feeds the second clock signal to the plurality of memory instances; and arranging a control circuit which selects the memory instances in synchronization with the first clock signal.

    摘要翻译： 提供了一种集成电路设计方法，其中将存储器实例分配给集成在集成电路内的存储器宏。 集成电路设计方法包括：将以相同操作频率操作的多个存储器实例分配给单个存储器宏; 布置频率倍增器，其接收第一时钟信号以通过第一时钟信号的倍频来产生第二时钟信号，并将第二时钟信号馈送到多个存储器实例; 以及布置与第一时钟信号同步地选择存储器实例的控制电路。