公开(公告)号：US20150015322A1

公开(公告)日：2015-01-15

申请号：US13938558

申请日：2013-07-10

Applicant: Astronics Advanced Electronic Systems Corp.

Inventor： Frederick J. Potter ,  Raymond Moravec

IPC: H03K17/687

CPC classification number: H03K17/122 ,  H03K2217/0036

Abstract: A solid state relay circuit is disclosed, containing a first and second group of FETs, the groups being connected in parallel. The first FET group contains commutation FETs capable of handling the commutation load of the circuit. The second FET group contains secondary FETs of lower resistance than the commutation FETs. The circuit is configured such that, when the circuit is activated, the commutation FETs are driven on before the secondary FETs. The circuit is also configured such that, when the circuit is deactivated, the commutation FETs are driven off only after the secondary FETs.

Abstract translation: 公开了一种固态继电器电路，其包含第一和第二组FET，所述组并联连接。 第一个FET组包含能够处理电路的换向负载的换向FET。 第二FET组包含比换向FET低的电阻的次级FET。 电路被配置为使得当电路被激活时，在次级FET之前驱动换向FET。 电路也被配置为使得当电路被去激活时，仅在次级FET之后驱动换向FET。

公开(公告)号：US08933746B1

公开(公告)日：2015-01-13

申请号：US13938558

申请日：2013-07-10

Applicant: Astronics Advanced Electronic Systems Corp.

Inventor： Frederick J. Potter ,  Raymond Moravec

IPC: H03K17/687

CPC classification number: H03K17/122 ,  H03K2217/0036

Abstract: A solid state relay circuit is disclosed, containing a first and second group of FETs, the groups being connected in parallel. The first FET group contains commutation FETs capable of handling the commutation load of the circuit. The second FET group contains secondary FETs of lower resistance than the commutation FETs. The circuit is configured such that, when the circuit is activated, the commutation FETs are driven on before the secondary FETs. The circuit is also configured such that, when the circuit is deactivated, the commutation FETs are driven off only after the secondary FETs.

Abstract translation: 公开了一种固态继电器电路，其包含第一和第二组FET，所述组并联连接。 第一个FET组包含能够处理电路的换向负载的换向FET。 第二FET组包含比换向FET低的电阻的次级FET。 电路被配置为使得当电路被激活时，在次级FET之前驱动换向FET。 电路也被配置为使得当电路被去激活时，仅在次级FET之后驱动换向FET。