公开(公告)号：US20170255396A1

公开(公告)日：2017-09-07

申请号：US15057145

申请日：2016-03-01

Applicant: Apple Inc.

Inventor： Yoni Labenski ,  Roman Gindin ,  Etai Zaltsman ,  Moti Altahan ,  Yoram Harel ,  Barak Baum

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0688

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.

公开(公告)号：US09952779B2

公开(公告)日：2018-04-24

申请号：US15057145

申请日：2016-03-01

Applicant: Apple Inc.

Inventor： Yoni Labenski ,  Roman Gindin ,  Etai Zaltsman ,  Moti Altahan ,  Yoram Harel ,  Barak Baum

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0688

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.