公开(公告)号：US10241557B2

公开(公告)日：2019-03-26

申请号：US14104042

申请日：2013-12-12

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ronald P Hall ,  Ramesh B Gunna ,  Ian D Kountanis ,  Shyam Sundar ,  André Seznec

IPC: G06F9/38 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296

Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.