公开(公告)号：US20250060939A1

公开(公告)日：2025-02-20

申请号：US18452373

申请日：2023-08-18

Applicant: Apple Inc.

Inventor： Yildiz SINANGIL ,  Lei WANG ,  Michael L LIU ,  Jaewon SHIN

IPC: G06F7/544

Abstract: The present disclosure describes an in-memory computing (IMC) circuit including a first set of IMC cells having a first number of IMC cells and a second set of IMC cells having the first number of IMC cells. The first set of IMC cells can generate a first bit-product of a weight number having a first number of bits and a first bit of an input number having a second number of bits. The second set of IMC cells can generate a second bit-product of the weight number and a second bit of the input number. A first IMC cell of the first set of IMC cells includes a first bit-wise multiplication circuit configured to multiply a first bit of the weight number and the first bit of the input number.