公开(公告)号：US10725928B1

公开(公告)日：2020-07-28

申请号：US16243901

申请日：2019-01-09

Applicant: Apple Inc.

Inventor： Brian R. Mestan ,  Pradeep Kanapathipillai ,  Joshua William Smith

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/1045

Abstract: A system and method for efficiently performing maintenance on a cache. In various embodiments, control logic in a cache controller or elsewhere receives an indication for invalidating a range of virtual-to-physical mappings in a given translation lookaside buffer (TLB). The logic determines a first latency to invalidate entries of the TLB based on a number of addresses in the range and a number of supported page sizes simultaneously stored in the TLB. The logic determines a second latency based on a number of entries in the TLB. If the first latency is greater, then the logic traverses through each TLB entry and invalidates TLB entries storing a virtual address within the range. If the first latency is smaller, then the logic traverses through each address in the range and invalidates TLB entries storing a virtual address within the range.

公开(公告)号：US20200218663A1

公开(公告)日：2020-07-09

申请号：US16243901

申请日：2019-01-09

Applicant: Apple Inc.

Inventor： Brian R. Mestan ,  Pradeep Kanapathipillai ,  Joshua William Smith

IPC: G06F12/0891 ,  G06F12/1045

Abstract: A system and method for efficiently performing maintenance on a cache. In various embodiments, control logic in a cache controller or elsewhere receives an indication for invalidating a range of virtual-to-physical mappings in a given translation lookaside buffer (TLB). The logic determines a first latency to invalidate entries of the TLB based on a number of addresses in the range and a number of supported page sizes simultaneously stored in the TLB. The logic determines a second latency based on a number of entries in the TLB. If the first latency is greater, then the logic traverses through each TLB entry and invalidates TLB entries storing a virtual address within the range. If the first latency is smaller, then the logic traverses through each address in the range and invalidates TLB entries storing a virtual address within the range.