公开(公告)号：US11004482B1

公开(公告)日：2021-05-11

申请号：US16784030

申请日：2020-02-06

Applicant: Apple Inc.

Inventor： Jaemyung Lim ,  Jiangyi Li ,  Mohamed H. Abu-Rahma ,  Shahzad Nazar ,  Jaroslav Raszka

IPC: G06F1/00 ,  G11C5/14

Abstract: Memory circuits used in computer systems may have different operating modes. In a retention mode, a voltage level of an array power supply node coupled to memory cells included in the memory circuit is reduced to a level sufficient to retain data, but not to perform read and write operations to the memory cells. A power converter circuit may be configured to generate the retention voltage level, and adjust the retention voltage level using a leakage current of dummy memory cells included in the memory circuit.