公开(公告)号：US20230040310A1

公开(公告)日：2023-02-09

申请号：US17392929

申请日：2021-08-03

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  Bryan R. HINCH ,  Ronit BANERJEE ,  Kushal DALMIA ,  Daniel A. CHIMENE ,  Jaidev P. PATWARDHAN

IPC: G06F9/50

Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having a first central processing unit (CPU) cluster comprising a first core type, and a second CPU cluster comprising a second core type, where the AMP system can update a thread metric for a first thread running on the first CPU cluster based at least on: a past shared resource overloaded metric of the first CPU cluster, and on-core metrics of the first thread. The on-core metrics of the first thread can indicate that first thread contributes to contention of the same shared resource corresponding to the past shared resource overloaded metric of the first CPU cluster. The AMP system can assign the first thread to a different CPU cluster while other threads of the same thread group remain assigned to the first CPU cluster. The thread metric can include a Matrix Extension (MX) thread flag or a Bus Interface Unit (BIU) thread flag.

公开(公告)号：US20230067109A1

公开(公告)日：2023-03-02

申请号：US17893913

申请日：2022-08-23

Applicant: Apple Inc.

Inventor： Bryan R. HINCH ,  John G. DORSEY ,  Ronit BANERJEE ,  Kushal DALMIA ,  Daniel A. CHIMENE ,  Jaidev P. PATWARDHAN

IPC: G06F15/78 ,  G06F11/34 ,  G06F9/48

Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.