公开(公告)号：US20250103520A1

公开(公告)日：2025-03-27

申请号：US18819755

申请日：2024-08-29

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Jurgen M. Schulz ,  Tom Greenshtein ,  Elli Bagelman ,  Brian P. Lilly ,  John H. Kelm ,  Rohit K. Gupta ,  Sandeep Gupta ,  Anwar Q. Rohillah

IPC: G06F13/16 ,  G06F12/0831

Abstract: A memory controller circuit receives memory access requests from a network of a computer system. Entries are reserved for these requests in a retry queue circuit. An arbitration circuit of the memory controller circuit issues those requests to a tag pipeline circuit that determines whether the received memory access requests hit in a memory cache. As a memory access request passes through the tag pipeline circuit, it may require another pass through this pipeline—for example, if resources such as certain storage circuits needed to complete the memory access request are unavailable (for example a snoop queue circuit). The reservation that has been made in the retry queue circuit thus keeps the request from having to be returned to the network for resubmission to the memory controller circuit if initial processing of the memory access request cannot be completed.

公开(公告)号：US20250103477A1

公开(公告)日：2025-03-27

申请号：US18819877

申请日：2024-08-29

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Jurgen M. Schulz ,  Tom Greenshtein ,  Elli Bagelman

IPC: G06F12/02 ,  G06F12/0815 ,  G06F12/12

Abstract: A memory controller circuit manages access to a memory cache circuit and storage circuits. The memory controller receives a memory access request, and attempts to reserve entries in a first set of storage circuits that are needed to process a cache hit prior to determining whether the memory access request hits in the memory cache circuit. This reservation attempt is performed without attempting to reserve other sets of storage circuits that are needed to process other possible outcomes of the memory access request, including a cache miss. If the memory controller circuit has successfully reserved entries in all of the first set of storage circuits, processing of the memory access request may be initiated. Conversely, if the memory controller is unable to reserve an entry in at least one of the first set of storage circuits, processing of the memory access request is inhibited.

公开(公告)号：US20230060508A1

公开(公告)日：2023-03-02

申请号：US17462374

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Elli Bagelman

IPC: G06F9/46 ,  G06F9/50 ,  G06F13/16

Abstract: A memory controller with a separate transaction table for real-time transactions is disclosed. A system includes a plurality of agents and a memory controller configured to receive real-time and non-real-time memory requests from ones of the plurality of agents. The memory controller includes a real-time incoming transaction table configured to store those memory requests received from a subset of the plurality of agents that are real-time memory requests, and a non-real-time incoming transaction table configured to store those memory requests received from the subset of the plurality of agents that are non-real-time memory requests. The memory controller further includes an arbitration circuit configured to select a memory request from among memory requests stored in the real-time and non-real-time incoming transaction tables and further configured to enforce a quality of service policy for the real-time memory requests.

公开(公告)号：US11900146B2

公开(公告)日：2024-02-13

申请号：US17462374

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Elli Bagelman

IPC: G06F9/46 ,  G06F13/16 ,  G06F9/50

CPC classification number: G06F9/467 ,  G06F9/5016 ,  G06F13/1605 ,  G06F2209/5011

Abstract: A memory controller with a separate transaction table for real-time transactions is disclosed. A system includes a plurality of agents and a memory controller configured to receive real-time and non-real-time memory requests from ones of the plurality of agents. The memory controller includes a real-time incoming transaction table configured to store those memory requests received from a subset of the plurality of agents that are real-time memory requests, and a non-real-time incoming transaction table configured to store those memory requests received from the subset of the plurality of agents that are non-real-time memory requests. The memory controller further includes an arbitration circuit configured to select a memory request from among memory requests stored in the real-time and non-real-time incoming transaction tables and further configured to enforce a quality of service policy for the real-time memory requests.