公开(公告)号：US10438683B2

公开(公告)日：2019-10-08

申请号：US15810166

申请日：2017-11-13

Applicant: Apple Inc.

Inventor： Barak Sagiv ,  Einav Yogev ,  Eli Yazovitsky ,  Eyal Gurgi ,  Roi Solomon

IPC: G11C29/44 ,  G11C29/38 ,  G11C29/02

Abstract: A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.

公开(公告)号：US10146460B1

公开(公告)日：2018-12-04

申请号：US15716703

申请日：2017-09-27

Applicant: Apple Inc.

Inventor： Barak Baum ,  Barak Sagiv ,  Einav Yogev ,  Eyal Gurgi ,  Ariel Landau

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F11/002 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/108 ,  G06F11/3058 ,  G11C7/04 ,  G11C11/5642

Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

公开(公告)号：US20180349044A1

公开(公告)日：2018-12-06

申请号：US15716703

申请日：2017-09-27

Applicant: Apple Inc.

Inventor： Barak Baum ,  Barak Sagiv ,  Einav Yogev ,  Eyal Gurgi ,  Ariel Landau

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F11/002 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/108 ,  G06F11/3058 ,  G11C7/04 ,  G11C11/5642

Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

公开(公告)号：US20180075926A1

公开(公告)日：2018-03-15

申请号：US15810166

申请日：2017-11-13

Applicant: Apple Inc.

Inventor： Barak Sagiv ,  Einav Yogev ,  Eli Yazovitsky ,  Eyal Gurgi ,  Roi Solomon

IPC: G11C29/44 ,  G11C29/38

CPC classification number: G11C29/44 ,  G11C29/028 ,  G11C29/38

Abstract: A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.

公开(公告)号：US09847141B1

公开(公告)日：2017-12-19

申请号：US15225863

申请日：2016-08-02

Applicant: APPLE INC.

Inventor： Barak Sagiv ,  Einav Yogev ,  Eli Yazovitsky ,  Eyal Gurgi ,  Roi Solomon

IPC: G06F11/00 ,  G11C29/00 ,  G11C29/44 ,  G11C29/38

CPC classification number: G11C29/44 ,  G11C29/028 ,  G11C29/38

Abstract: A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.