Automatically Identifying Resettable Flops For Digital Designs
    1.
    发明申请
    Automatically Identifying Resettable Flops For Digital Designs 有权
    自动识别数字设计的可复位触发器

    公开(公告)号:US20140089873A1

    公开(公告)日:2014-03-27

    申请号:US13627653

    申请日:2012-09-26

    Applicant: APPLE INC.

    CPC classification number: G06F17/5022 G06F17/5045

    Abstract: An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all components that retain their state are reset at reset. The tests are run with a respective logic value (1 or 0) randomly assigned to each non-resettable component at reset, until a test run fails. The failed test is rerun a specified number of times, each time with a different set of randomly assigned logic values provided to non-resettable components at reset. For each run, statistics are logged for each non-resettable component according to the test results and the logic value provided to the non-resettable component. The process determines which non-resettable components need to be resettable according to the statistics.

    Abstract translation: 自动化过程确定哪些组件保留其状态需要在设计中重置。 分析设计以识别保持其状态并且不可重置的组件。 在设计上运行一组仿真测试,当所有保持其状态的组件在复位时都被复位时,每个测试都会被传递。 测试在复位时随机分配给每个不可复位组件的相应逻辑值(1或0)运行,直到测试运行失败。 失败的测试重新运行指定的次数,每次在复位时向不可复位组件提供不同的随机分配逻辑值集合。 对于每个运行,根据测试结果和提供给不可重置组件的逻辑值,为每个不可重置组件记录统计信息。 该过程根据统计信息确定哪些不可复位组件需要重置。

    Automatically identifying resettable flops for digital designs
    2.
    发明授权
    Automatically identifying resettable flops for digital designs 有权
    自动识别数字设计的可复位触发器

    公开(公告)号:US08869080B2

    公开(公告)日:2014-10-21

    申请号:US13627653

    申请日:2012-09-26

    Applicant: Apple Inc.

    CPC classification number: G06F17/5022 G06F17/5045

    Abstract: An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all components that retain their state are reset at reset. The tests are run with a respective logic value (1 or 0) randomly assigned to each non-resettable component at reset, until a test run fails. The failed test is rerun a specified number of times, each time with a different set of randomly assigned logic values provided to non-resettable components at reset. For each run, statistics are logged for each non-resettable component according to the test results and the logic value provided to the non-resettable component. The process determines which non-resettable components need to be resettable according to the statistics.

    Abstract translation: 自动化过程确定哪些组件保留其状态需要在设计中重置。 分析设计以识别保持其状态并且不可重置的组件。 在设计上运行一组仿真测试,当所有保持其状态的组件在复位时都被复位时,每个测试都会被传递。 测试在复位时随机分配给每个不可复位组件的相应逻辑值(1或0)运行,直到测试运行失败。 失败的测试重新运行指定的次数,每次在复位时向不可复位组件提供不同的随机分配逻辑值集合。 对于每个运行,根据测试结果和提供给不可重置组件的逻辑值,为每个不可重置组件记录统计信息。 该过程根据统计信息确定哪些不可复位组件需要重置。

    Testing a Hardware Emulation Model of a Circuit with Software Checker Routines Designed for an RTL Model of the Circuit
    3.
    发明申请
    Testing a Hardware Emulation Model of a Circuit with Software Checker Routines Designed for an RTL Model of the Circuit 审中-公开
    使用针对电路RTL模型设计的软件检查程序来测试电路的硬件仿真模型

    公开(公告)号:US20140100841A1

    公开(公告)日:2014-04-10

    申请号:US13647742

    申请日:2012-10-09

    Applicant: APPLE INC.

    CPC classification number: G06F17/5027

    Abstract: A hardware emulation system may emulate a plurality of cycles of a circuit, and may store state information at each cycle which specifies signal values for one or more signals of the circuit. After the hardware emulation has finished, the state information may be streamed from the memory of the hardware emulation system to a different storage device that is accessible by a computer system that executes one or more software checker routines. The computer system may execute the software checker routines, which may include passing the signal values specified in the state information to the software checker routines on a cycle-by-cycle basis similarly as if the software checker routines were receiving them in real time directly from the hardware emulation system.

    Abstract translation: 硬件仿真系统可以模拟电路的多个周期,并且可以在每个周期存储指定电路的一个或多个信号的信号值的状态信息。 在硬件仿真完成之后,状态信息可以从硬件仿真系统的存储器流传输到由执行一个或多个软件检查程序的计算机系统可访问的不同的存储设备。 计算机系统可以执行软件检查程序,其可以包括将状态信息中指定的信号值逐个循环地传递给软件检查程序,类似于软件检查程序直接从 硬件仿真系统。

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