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1.发明授权Adjustable elasticity FIFO buffer have a number of storage cells equal to a frequency offset times a number of data units in a data stream 有权可调弹性FIFO缓冲器具有等于数据流中多个数据单元的频率偏移的多个存储单元公开(公告)号：US07234007B2
公开(公告)日：2007-06-19
申请号：US10811126
申请日：2004-03-29
CPC分类号： G06F5/12 , G06F2205/063
摘要： A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.
摘要翻译： 根据写时钟和读时钟来执行通过缓冲器处理数据流的方法。 缓冲器具有多个顺序编号的存储单元。 该方法包括以下步骤：选择步骤包括确定写入和读取时钟之间的最大频率偏移的乘积以及数据流中的任意符号之间的最大时间。 然后，存储单元响应于写指针接收数据单元。 然后响应于读指针从存储单元提供数据单元。
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2.发明授权Adjustable elasticity FIFO buffer with preload value having a number of storage cells equal to frequency offset times between data units in a data stream 失效具有预加载值的可调节弹性FIFO缓冲器，其具有等于数据流中的数据单元之间的频率偏移时间的多个存储单元公开(公告)号：US08041853B2
公开(公告)日：2011-10-18
申请号：US11798467
申请日：2007-05-14
CPC分类号： G06F5/12 , G06F2205/063
摘要： A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.
摘要翻译： 根据写时钟和读时钟来执行通过缓冲器处理数据流的方法。 缓冲器具有多个顺序编号的存储单元。 该方法包括以下步骤：选择步骤包括确定写入和读取时钟之间的最大频率偏移的乘积以及数据流中的任意符号之间的最大时间。 然后，存储单元响应于写指针接收数据单元。 然后响应于读指针从存储单元提供数据单元。
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3.发明申请公开(公告)号：US20050254491A1
公开(公告)日：2005-11-17
申请号：US11157718
申请日：2005-06-21
申请人： John Lenell , David Fisher , Andrew Castellano
发明人： John Lenell , David Fisher , Andrew Castellano
CPC分类号： H04L12/5601 , H04J3/0608 , H04L7/042 , H04L49/455 , H04L69/12 , H04L69/22 , H04L2012/5679
摘要： Each packet normally consists of a preamble, start-of-frame delimiter and data. The preamble has nibbles each having a particular format. A header substituted for preamble nibbles by an individual one of the originating devices in a plurality, and an individual one of the ports in such originating device, indicates such originating device and such port. Such port in such originating device sends such modified packet to others of the originating devices and to an observing station. The header format is such that the last nibble in the header and the remaining preamble portion will not be confused with any two (2) nibbles in the header. A particular one of the originating devices indicated in the data converts the header back to the preamble format and transmits the converted packet to a receiving station. The observing station records the individual originating device, and the individual port in such device, indicated in the header. Each packet includes at its end a trailer formed from a plurality of nibbles and indicating whether or not a collision has occurred between such packet and a packet from another one of the originating devices. The trailer in each packet may also indicate additional information—e.g. whether the packet (a) is a normal packet originally formed, (b) is a runt packet, (c) is from an unacceptable source and (d) the delay between each packet end and the next packet start. The information in the trailer for each packet passes to the observing station.
摘要翻译： 每个分组通常由前导码，帧起始分隔符和数据组成。 前导码具有各自具有特定格式的半字节。 由多个发端设备中的一个单独的一个替换前同步码的头部以及这种始发设备中的各个端口中的单独的一个表示这种始发设备和这样的端口。 这种始发设备中的这种端口将这种修改的分组发送到始发设备的其他设备和观测站。 标题格式使得报头和剩余前导码部分中的最后一个半字节不会与报头中的任何两个（2）半字节混淆。 数据中指示的特定一个始发设备将报头转换回前导码格式并将转换的分组发送到接收站。 观察站记录单个发起设备，以及在该设备中的单个端口，标题中指示。 每个分组在其末尾包括由多个半字节形成的预告，并且指示在这样的分组与来自另一个始发设备的分组之间是否发生了冲突。 每个分组中的预告片也可以指示附加信息 - 例如 分组（a）是否是原始形成的正常分组，（b）是分组分组，（c）来自不可接受的源，（d）每个分组结束与下一个分组开始之间的延迟。 每个包的预告片中的信息传递到观察站。
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公开(公告)号：US20070214291A1
公开(公告)日：2007-09-13
申请号：US11798467
申请日：2007-05-14
申请人： Andrew Castellano , Pinghua Yang
发明人： Andrew Castellano , Pinghua Yang
IPC分类号： G06F3/00
CPC分类号： G06F5/12 , G06F2205/063
摘要： A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.
摘要翻译： 根据写时钟和读时钟来执行通过缓冲器处理数据流的方法。 缓冲器具有多个顺序编号的存储单元。 该方法包括以下步骤：选择步骤包括确定写入和读取时钟之间的最大频率偏移的乘积以及数据流中的任意符号之间的最大时间。 然后，存储单元响应于写指针接收数据单元。 然后响应于读指针从存储单元提供数据单元。
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公开(公告)号：US20060143490A1
公开(公告)日：2006-06-29
申请号：US11358148
申请日：2006-02-21
IPC分类号： G06F1/04
CPC分类号： H04L7/0008 , H04L7/0037
摘要： Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a transmitted and/or a received signal. The operational parameters including frequency and phase may be determined during auto detect/auto negotiation, they may be programmed externally, or they may be user selected in various embodiments. A device may include a clock generator, one or more divider, and one or more delay cells internally to the device. If desired, a high frequency clock is generated within the device and then divided down to generate the appropriate clock signal that supports the communication and interaction between multiple devices. Registers and/or pins may be used to select the clock frequency and phase of output clock signals. The present invention supports multiple Ethernet protocols between multiple devices including 10BaseT, 100BaseT, and 1000BaseT.
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公开(公告)号：US20060114833A1
公开(公告)日：2006-06-01
申请号：US11332937
申请日：2006-01-17
申请人： Andrew Castellano , Gary Huff
发明人： Andrew Castellano , Gary Huff
IPC分类号： H04J3/14
CPC分类号： H04L1/20
摘要： A method and apparatus for generating a performance indicator in a high-speed communication system. A plurality of disparate communication status signals with differing formats from a transceiver are combined in a logic module to create a single link quality indicator signal. The link quality indicator signal is used to encode different operational states of the transceiver from fully operational, to marginally operational, to failed. The link quality indicator signal is advantageously employed to drive a LED creating a visual performance indicator.
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公开(公告)号：US20050058148A1
公开(公告)日：2005-03-17
申请号：US10811126
申请日：2004-03-29
申请人： Andrew Castellano , Pinghua Yang
发明人： Andrew Castellano , Pinghua Yang
CPC分类号： G06F5/12 , G06F2205/063
摘要： A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.
摘要翻译： 根据写时钟和读时钟来执行通过缓冲器处理数据流的方法。 缓冲器具有多个顺序编号的存储单元。 该方法包括以下步骤：选择步骤包括确定写入和读取时钟之间的最大频率偏移的乘积以及数据流中的任意符号之间的最大时间。 然后，存储单元响应于写指针接收数据单元。 然后响应于读指针从存储单元提供数据单元。
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