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1.发明授权Methods and apparatus related to data processors and caches incorporated in data processors 有权与数据处理器相关的方法和设备，以及并入数据处理器中的高速缓存公开(公告)号：US09317448B2
公开(公告)日：2016-04-19
申请号：US13953835
申请日：2013-07-30
Applicant: Advanced Micro Devices, Inc.
CPC classification number: G06F12/123 , G06F12/0804 , G06F12/12 , G06F12/121 , G06F2212/1024
Abstract: A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.
Abstract translation: 高速缓存包括高速缓存阵列和高速缓存控制器。 缓存阵列具有多个条目。 高速缓存控制器被耦合到高速缓存阵列，用于响应于数据处理器的访问来存储高速缓存阵列中的新条目，并根据高速缓存替换策略从高速缓存阵列中取出条目。 高速缓存控制器包括用于存储指示多个条目的回写频率的频率信息的频繁写入预测器。 高速缓存控制器基于新近度信息和频率信息来选择用于驱逐的候选条目。
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2.发明申请METHODS AND APPARATUS RELATED TO DATA PROCESSORS AND CACHES INCORPORATED IN DATA PROCESSORS 有权与数据处理器中的数据处理器和缓存相关的方法和设备公开(公告)号：US20150039836A1
公开(公告)日：2015-02-05
申请号：US13953835
申请日：2013-07-30
Applicant: Advanced Micro Devices, Inc.
IPC: G06F12/12
CPC classification number: G06F12/123 , G06F12/0804 , G06F12/12 , G06F12/121 , G06F2212/1024
Abstract: A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.
Abstract translation: 高速缓存包括高速缓存阵列和高速缓存控制器。 缓存阵列具有多个条目。 高速缓存控制器被耦合到高速缓存阵列，用于响应于数据处理器的访问来存储高速缓存阵列中的新条目，并根据高速缓存替换策略从高速缓存阵列中取出条目。 高速缓存控制器包括用于存储指示多个条目的回写频率的频率信息的频繁写入预测器。 高速缓存控制器基于新近度信息和频率信息来选择用于驱逐的候选条目。
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