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公开(公告)号：US20180374853A1
公开(公告)日：2018-12-27
申请号：US15632765
申请日：2017-06-26
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Erhan Ergin , Dipanjan Sengupta , Elsie Lo , Stephen V. Kosonocky , Sree Rajesh Saha , Divya Guruja
Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.
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公开(公告)号：US10218273B2
公开(公告)日：2019-02-26
申请号：US15632765
申请日：2017-06-26
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Erhan Ergin , Dipanjan Sengupta , Elsie Lo , Stephen V. Kosonocky , Sree Rajesh Saha , Divya Guruja
IPC: H02M3/158
Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.
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公开(公告)号：US20190004588A1
公开(公告)日：2019-01-03
申请号：US15639992
申请日：2017-06-30
Applicant: ATI Technologies ULC
Inventor： Elsie Lo , Erhan Ergin , Dipanjan Sengupta , Rajit Seahra , Sowmya Thikkavarapu , Kameswara Goutham Vankayalapati
IPC: G06F1/32
CPC classification number: G06F17/5081 , G06F1/3243 , G06F1/3296 , G06F2217/78
Abstract: A non-transitory computer-readable medium includes instructions that, when provided to and executed by a processor, cause the processor to receive a first placement of domain instances of an integrated circuit layout provided as a tile having a group of multiple power domain modules. The first placement of domain instances is scanned to identify instances associated with a preselected power specification. A heuristic is applied to the first placement of domain instances to form an observation area. the heuristic demarcates select instances to form the observation area. Each instance associated with the preselected power specification is identified in the observation area. A contiguous region of instances is formed from the select instances in the observation area. The first placement of domain instances in the integrated circuit layout is modified to provided revised placement for instances associated with the contiguous region of instances.
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公开(公告)号：US10515182B2
公开(公告)日：2019-12-24
申请号：US15639992
申请日：2017-06-30
Applicant: ATI Technologies ULC
Inventor： Elsie Lo , Erhan Ergin , Dipanjan Sengupta , Rajit Seahra , Sowmya Thikkavarapu , Kameswara Goutham Vankayalapati
IPC: G06F17/50 , G06F1/3296 , G06F1/3234
Abstract: A non-transitory computer-readable medium includes instructions that, when provided to and executed by a processor, cause the processor to receive a first placement of domain instances of an integrated circuit layout provided as a tile having a group of multiple power domain modules. The first placement of domain instances is scanned to identify instances associated with a preselected power specification. A heuristic is applied to the first placement of domain instances to form an observation area. The heuristic demarcates select instances to form the observation area. Each instance associated with the preselected power specification is identified in the observation area. A contiguous region of instances is formed from the select instances in the observation area. The first placement of domain instances in the integrated circuit layout is modified to provided revised placement for instances associated with the contiguous region of instances.
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