CODING FOR PULSE AMPLITUDE MODULATION WITH AN ODD NUMBER OF OUTPUT LEVELS

    公开(公告)号:US20240305287A1

    公开(公告)日:2024-09-12

    申请号:US18664505

    申请日:2024-05-15

    Applicant: APPLE INC.

    CPC classification number: H03K9/02 H03K7/02

    Abstract: The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

    Coding for pulse amplitude modulation with an odd number of output levels

    公开(公告)号:US12015413B2

    公开(公告)日:2024-06-18

    申请号:US17945429

    申请日:2022-09-15

    Applicant: Apple Inc.

    CPC classification number: H03K9/02 H03K7/02

    Abstract: The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

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