公开(公告)号：US20150372682A1

公开(公告)日：2015-12-24

申请号：US14745017

申请日：2015-06-19

Applicant: ANALOG DEVICES, INC.

Inventor： ALEXANDER A. ALEXEYEV ,  ERIC G. NESTLER

IPC: H03L7/08

CPC classification number: H03L7/085

Abstract: An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.

Abstract translation: 集成电路实现了锁相环（PLL）的至少一部分。 集成电路包括用于PLL的采样模拟环路滤波器。 环路滤波器包括用于接收表示参考时钟信号和第一时钟信号之间的相位差的信号的第一输入端，用于提供用于控制振荡器频率的频率控制信号的第一输出端，​​用于接收振荡器的时钟输入 环路定时时钟信号，用于控制环路滤波器的操作定时;以及数字控制输入，用于根据多个控制值配置环路滤波器的响应。 在一些示例中，环路滤波器包括通过可控开关耦合的电荷存储元件和用于在电荷存储元件之间传送电荷的控制电路，以产生环路滤波器的配置响应。