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    SIMPLIFIED LOW-PRECISION RAY INTERSECTION THROUGH ACCELERATED HIERARCHY STRUCTURE PRECOMPUTATION
    2.
    发明申请
    SIMPLIFIED LOW-PRECISION RAY INTERSECTION THROUGH ACCELERATED HIERARCHY STRUCTURE PRECOMPUTATION 有权

    公开(公告)号：US20250111587A1

    公开(公告)日：2025-04-03

    申请号：US18478259

    申请日：2023-09-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Andrew Erin Kensler ,  Sean Keely ,  Michael John Livesley ,  David William John Pankratz

    IPC: G06T15/06 ,  G06T17/00

    Abstract: Devices and methods for rendering objects using ray tracing are provided which include during a build time: generating an accelerated hierarchy structure comprising data representing an approximate volume bounding a group of geometric shapes representing the objects in the scene and data representing the geometric shapes; and generating additional data used to transform rays, to be cast in the scene, from a high precision space to a low precision space; and during a render time occurring after the build time: performing ray intersection tests, using the additional data generated during the build time, for the rays in the scene; and rendering the scene based on the ray intersection tests. Because the additional data is generated prior to render time, the additional data can be used to perform the ray intersection testing more efficiently.

    STREAMING WAVE COALESCER CIRCUIT
    3.
    发明申请
    STREAMING WAVE COALESCER CIRCUIT 有权

    公开(公告)号：US20250068429A1

    公开(公告)日：2025-02-27

    申请号：US18536982

    申请日：2023-12-12

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Stephen Junkins ,  Christopher J. Brennan ,  Ian Richard Beaumont ,  Kellie Marks ,  Matthaeus G. Chajdas ,  Max Oberberger ,  Michael John Bedy ,  Michael Mantor ,  Sean Keely

    IPC: G06F9/38

    Abstract: A Streaming Wave Coalescer (SWC) circuit stores a first set of state values associated with a first subset of threads of a first wave in a bin based on each of the first subset of threads including a first set of instructions to be executed. A second set of state values associated with a second subset of threads of a second wave is stored in the bin based on each of the second subset of threads including the first set of instructions to be executed and based on the first wave and the second wave both being associated with a hard key. A third wave is formed from the threads of the first subset and the second subset and is emitted for execution. As a result of reorganizing the threads and reconstituting a different wave, thread divergence of waves sent for execution is reduced.

    Spill-After Programming Model for the Streaming Wave Coalescer
    6.
    发明申请
    Spill-After Programming Model for the Streaming Wave Coalescer 有权

    公开(公告)号：US20250130811A1

    公开(公告)日：2025-04-24

    申请号：US18895737

    申请日：2024-09-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sean Keely ,  Kellie Marks

    IPC: G06F9/38 ,  G06F15/80

    Abstract: An apparatus and method for efficiently migrating the execution of threads between multiple parallel lanes of execution. In various implementations, a computing system includes multiple vector processing circuits of a compute circuit that executes multiple lanes of multiple waves. Each lane includes a key indicating a path of execution. When a lane of the multiple lanes of execution executes a stream wave coalescing (SWC) reorder instruction, a control circuit compares keys of waves that have previously executed the SWC reorder instruction. When the number of lanes with a matching key exceeds a threshold and after identifying at least this number of lanes to swap, the control circuit swaps continuation state information (live active state information) between lanes of an emitting wave that do not have a matching key and lanes of contributing waves that do have a matching key. The resulting (reordered) emitting wave executes more efficiently, which increases performance.

    BUILDING KD-TREES IN A DEPTH FIRST MANNER ON HETEROGENEOUS COMPUTER SYSTEMS
    8.
    发明申请
    BUILDING KD-TREES IN A DEPTH FIRST MANNER ON HETEROGENEOUS COMPUTER SYSTEMS 审中-公开
    在异源计算机系统中建立一个深度第一的人的KD-TREES

    公开(公告)号：US20130328876A1

    公开(公告)日：2013-12-12

    申请号：US13912791

    申请日：2013-06-07

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sean Keely

    IPC: G06T15/06

    CPC classification number: G06T15/06 ,  G06T17/005 ,  G06T2210/52

    Abstract: Apparatuses, computer readable mediums, and methods of building a k-dimensional tree (kd-tree) are disclosed. The method may include a first processor, for example a graphics processing unit (GPU), selecting a node to split in a depth first manner. The method may include the GPU splitting based on a split plane a node into a left node and a right node. The GPU may assign the left (right) node to the GPU when a number of polygons associated with the left (right) node is above a threshold and otherwise assign the left node to a second processor, for example a central processing unit (CPU). The CPU may build the kd-tree in a depth first manner. The GPU (CPU) may select a next node to split based on a last node assigned to the GPU (CPU) or by selecting a node that is currently in a local memory of the GPU (CPU).

    Abstract translation: 公开了装置，计算机可读介质和建立k维树（kd-tree）的方法。 该方法可以包括第一处理器，例如图形处理单元（GPU），以深度第一方式选择要分割的节点。 该方法可以包括基于将节点拆分成左节点和右节点的GPU分割。 当与左（右）节点相关联的多个多边形的数量高于阈值时，GPU可以将左（右）节点分配给GPU，否则将左节点分配给第二处理器，例如中央处理单元（CPU） 。 CPU可以以深度第一方式构建kd-tree。 GPU（CPU）可以基于分配给GPU（CPU）的最后节点或通过选择当前在GPU（CPU）的本地存储器中的节点来选择要分解的下一个节点。

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