公开(公告)号：US20210182213A1

公开(公告)日：2021-06-17

申请号：US16716165

申请日：2019-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Jieming Yin ,  Yasuko Eckert ,  Subhash Sethumurugan

IPC: G06F12/122

Abstract: Systems, apparatuses, and methods for implementing cache line re-reference interval prediction using a physical page address are disclosed. When a cache line is accessed, a controller retrieves a re-reference interval counter value associated with the line. If the counter is less than a first threshold, then the address of the cache line is stored in a small re-use page buffer. If the counter is greater than a second threshold, then the address is stored in a large re-use page buffer. When a new cache line is inserted in the cache, if its address is stored in the small re-use page buffer, then the controller assigns a high priority to the line to cause it to remain in the cache to be re-used. If a match is found in the large re-use page buffer, then the controller assigns a low priority to the line to bias it towards eviction.

公开(公告)号：US11797455B2

公开(公告)日：2023-10-24

申请号：US16600897

申请日：2019-10-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jieming Yin ,  Subhash Sethumurugan ,  Yasuko Eckert

IPC: G06F12/12 ,  G06F12/0891 ,  G06F12/0855 ,  G06F12/126 ,  G06F12/0897 ,  G06F12/0871

CPC classification number: G06F12/0891 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0897 ,  G06F12/126

Abstract: A cache of a processor includes a cache controller to implement a cache management policy for the insertion and replacement of cache lines of the cache. The cache management policy assigns replacement priority levels to each cache line of at least a subset of cache lines in a region of the cache based on a comparison of a number of accesses to a cache set having a way that stores a cache line since the cache line was last accessed to a reuse distance determined for the region of the cache, wherein the reuse distance represents an average number of accesses to a given cache set of the region between accesses to any given cache line of the cache set.

公开(公告)号：US11768779B2

公开(公告)日：2023-09-26

申请号：US16716194

申请日：2019-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Jieming Yin ,  Yasuko Eckert ,  Subhash Sethumurugan

IPC: G06F12/12 ,  G06F12/126

CPC classification number: G06F12/126 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/602

Abstract: Systems, apparatuses, and methods for cache management based on access type priority are disclosed. A system includes at least a processor and a cache. During a program execution phase, certain access types are more likely to cause demand hits in the cache than others. Demand hits are load and store hits to the cache. A run-time profiling mechanism is employed to find which access types are more likely to cause demand hits. Based on the profiling results, the cache lines that will likely be accessed in the future are retained based on their most recent access type. The goal is to increase demand hits and thereby improve system performance. An efficient cache replacement policy can potentially reduce redundant data movement, thereby improving system performance and reducing energy consumption.

公开(公告)号：US20210182216A1

公开(公告)日：2021-06-17

申请号：US16716194

申请日：2019-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Jieming Yin ,  Yasuko Eckert ,  Subhash Sethumurugan

IPC: G06F12/126

Abstract: Systems, apparatuses, and methods for cache management based on access type priority are disclosed. A system includes at least a processor and a cache. During a program execution phase, certain access types are more likely to cause demand hits in the cache than others. Demand hits are load and store hits to the cache. A run-time profiling mechanism is employed to find which access types are more likely to cause demand hits. Based on the profiling results, the cache lines that will likely be accessed in the future are retained based on their most recent access type. The goal is to increase demand hits and thereby improve system performance. An efficient cache replacement policy can potentially reduce redundant data movement, thereby improving system performance and reducing energy consumption.