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1.发明申请High speed ethernet MAC and PHY apparatus with a filter based ethernet packet router with priority queuing and single or multiple transport stream interfaces 有权具有优先级排队和单个或多个传输流接口的基于过滤器的以太网分组路由器的高速以太网MAC和PHY设备公开(公告)号：US20060174032A1
公开(公告)日：2006-08-03
申请号：US11046292
申请日：2005-01-28
IPC分类号： G06F15/173
CPC分类号： H04L45/00 , H04L12/4633 , H04L12/6418 , H04L47/2416
摘要： In one embodiment, an audio-visual content delivery system, such as a set-top box/personal video recorder system, is configured to interface with a local area network (LAN). A packet processing circuit comprised in the system may be configured to filter and route Ethernet packet data received from the LAN to specific ports and/or queues without host processor intervention. The packet processing circuit may utilize a set of filter and routing mechanisms configurable in hardware to interpret various Internet Engineering Task Force (IETF) networking transport protocols, and may transfer the packet data in a format recognized by a variety of consumer subsystems, each of which may be coupled to the decoder. The packet processing circuit may be implemented as a semiconductor device, and may allow encapsulated application data, (encapsulated using standardized encapsulation techniques), to be routed to a plurality of different types of application sinks or processors, forming a point-to-point or multi-point serial or parallel data stream over a standard transport covering numerous levels of the ISO data communications stack.
摘要翻译： 在一个实施例中，诸如机顶盒/个人录像机系统的视听内容传送系统被配置为与局域网（LAN）进行接口。 包括在系统中的分组处理电路可以被配置为在没有主机处理器干预的情况下将从LAN接收到的以太网分组数据过滤并路由到特定端口和/或队列。 分组处理电路可以利用在硬件中配置的一组过滤器和路由机制来解释各种因特网工程任务组（IETF）网络传输协议，并且可以以各种消费者子系统识别的格式传送分组数据，每个消费者子系统 可以耦合到解码器。 分组处理电路可以被实现为半导体器件，并且可以允许封装的应用数据（使用标准封装技术封装）被路由到多个不同类型的应用接收器或处理器，形成点对点或 跨标准传输的多点串行或并行数据流，覆盖ISO数据通信堆栈的多个级别。
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公开(公告)号：US20060095611A1
公开(公告)日：2006-05-04
申请号：US10979924
申请日：2004-11-02
申请人： Neil Winchester , William Chiechi , Paul Brant
发明人： Neil Winchester , William Chiechi , Paul Brant
IPC分类号： G06F5/00
CPC分类号： G06F13/28
摘要： A memory alignment system for efficient data transfer between a host system and a remote system comprises a data communications controller configured to align transmitted and received data based on formatting information received from the host system. When transmitting data from local system memory, for example over an Ethernet connection, communications control driver software may first write formatting information corresponding to the data into a configurable transmit data buffer. The data communications controller is operable to align the data based on the formatting information as the driver software moves the data into the transmit data buffer. Similarly, the driver software may write formatting information for receive data into a receive-format configuration buffer. The data communications controller may align the receive data based on the receive-formatting information as the receive data is being written into a configurable receive buffer. As the data communications controller performs all the required data alignment, no data alignment by the host processor is required.
摘要翻译： 用于在主机系统和远程系统之间有效数据传输的存储器对准系统包括数据通信控制器，其被配置为基于从主机系统接收的格式化信息对准发送和接收的数据。 当通过以太网连接从本地系统存储器发送数据时，通信控制驱动器软件可以首先将对应于数据的格式化信息写入可配置的发送数据缓冲器。 当驱动器软件将数据移动到发送数据缓冲器中时，数据通信控制器可操作以基于格式化信息对准数据。 类似地，驱动软件可以将用于接收数据的格式化信息写入接收格式配置缓冲器。 当接收数据被写入可配置的接收缓冲器时，数据通信控制器可以基于接收格式化信息对准接收数据。 由于数据通信控制器执行所有必需的数据对齐，因此不需要主处理器进行数据对齐。
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3.发明授权High speed ethernet MAC and PHY apparatus with a filter based ethernet packet router with priority queuing and single or multiple transport stream interfaces 有权具有优先级排队和单个或多个传输流接口的基于过滤器的以太网分组路由器的高速以太网MAC和PHY设备公开(公告)号：US08281031B2
公开(公告)日：2012-10-02
申请号：US11046292
申请日：2005-01-28
IPC分类号： G06F15/173
CPC分类号： H04L45/00 , H04L12/4633 , H04L12/6418 , H04L47/2416
摘要： In one embodiment, an audio-visual content delivery system, such as a set-top box/personal video recorder system, is configured to interface with a local area network (LAN). A packet processing circuit comprised in the system may be configured to filter and route Ethernet packet data received from the LAN to specific ports and/or queues without host processor intervention. The packet processing circuit may utilize a set of filter and routing mechanisms configurable in hardware to interpret various Internet Engineering Task Force (IETF) networking transport protocols, and may transfer the packet data in a format recognized by a variety of consumer subsystems, each of which may be coupled to the decoder. The packet processing circuit may be implemented as a semiconductor device, and may allow encapsulated application data, (encapsulated using standardized encapsulation techniques), to be routed to a plurality of different types of application sinks or processors, forming a point-to-point or multi-point serial or parallel data stream over a standard transport covering numerous levels of the ISO data communications stack.
摘要翻译： 在一个实施例中，诸如机顶盒/个人录像机系统的视听内容传送系统被配置为与局域网（LAN）进行接口。 包括在系统中的分组处理电路可以被配置为在没有主机处理器干预的情况下将从LAN接收到的以太网分组数据过滤并路由到特定端口和/或队列。 分组处理电路可以利用在硬件中配置的一组过滤器和路由机制来解释各种因特网工程任务组（IETF）网络传输协议，并且可以以各种消费者子系统识别的格式来传送分组数据，每个消费者子系统 可以耦合到解码器。 分组处理电路可以被实现为半导体器件，并且可以允许封装的应用数据（使用标准封装技术封装）被路由到多个不同类型的应用接收器或处理器，形成点对点或 跨标准传输的多点串行或并行数据流，覆盖ISO数据通信堆栈的多个级别。
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4.发明授权High speed ethernet MAC and PHY apparatus with a filter based ethernet packet router with priority queuing and single or multiple transport stream interfaces 有权具有优先级排队和单个或多个传输流接口的基于过滤器的以太网分组路由器的高速以太网MAC和PHY设备公开(公告)号：US08880728B2
公开(公告)日：2014-11-04
申请号：US13607022
申请日：2012-09-07
IPC分类号： G06F15/173 , H04L12/64 , H04L12/46 , H04L12/853 , H04L12/701
CPC分类号： H04L45/00 , H04L12/4633 , H04L12/6418 , H04L47/2416
摘要： An audio-visual content delivery system includes an interface to communicate with a local area network (LAN). A packet processing circuit in the system may filter and route Ethernet packet data received from the LAN, to specific ports and/or queues without host processor intervention. The packet processing circuit may utilize a set of filter and routing mechanisms configurable in hardware to interpret various Internet Engineering Task Force networking transport protocols, and may transfer the packet data in a format recognized by a variety of consumer subsystems, each of which may be coupled to the packet processing circuit. The packet processing circuit may be implemented as a semiconductor device, and may allow encapsulated application data to be routed to a plurality of different types of application sinks or processors, forming a point-to-point or multi-point serial or parallel data stream over a standard transport covering numerous levels of the ISO data communications stack.
摘要翻译： 视听内容传送系统包括与局域网（LAN）通信的接口。 系统中的分组处理电路可以将从LAN接收到的以太网分组数据过滤和路由到特定端口和/或队列，而无需主机处理器干预。 分组处理电路可以利用在硬件中配置的一组过滤器和路由机制来解释各种互联网工程任务组网络传输协议，并且可以以各种消费者子系统识别的格式传送分组数据，每个消费者子系统可以耦合 到分组处理电路。 分组处理电路可以被实现为半导体器件，并且可以允许封装的应用数据被路由到多个不同类型的应用接收器或处理器，形成点对点或多点串行或并行数据流 标准的传输涵盖了ISO数据通信栈的多个层次。
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5.发明申请High Speed Ethernet MAC and PHY Apparatus with a Filter Based Ethernet Packet Router with Priority Queuing and Single or Multiple Transport Stream Interfaces 有权具有优先级排队和单个或多个传输流接口的基于过滤器的以太网分组路由器的高速以太网MAC和PHY设备公开(公告)号：US20130010795A1
公开(公告)日：2013-01-10
申请号：US13607022
申请日：2012-09-07
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L12/4633 , H04L12/6418 , H04L47/2416
摘要： An audio-visual content delivery system includes an interface to communicate with a local area network (LAN). A packet processing circuit in the system may filter and route Ethernet packet data received from the LAN, to specific ports and/or queues without host processor intervention. The packet processing circuit may utilize a set of filter and routing mechanisms configurable in hardware to interpret various Internet Engineering Task Force networking transport protocols, and may transfer the packet data in a format recognized by a variety of consumer subsystems, each of which may be coupled to the packet processing circuit. The packet processing circuit may be implemented as a semiconductor device, and may allow encapsulated application data to be routed to a plurality of different types of application sinks or processors, forming a point-to-point or multi-point serial or parallel data stream over a standard transport covering numerous levels of the ISO data communications stack.
摘要翻译： 视听内容传送系统包括与局域网（LAN）通信的接口。 系统中的分组处理电路可以将从LAN接收到的以太网分组数据过滤和路由到特定端口和/或队列，而无需主机处理器干预。 分组处理电路可以利用在硬件中配置的一组过滤器和路由机制来解释各种互联网工程任务组网络传输协议，并且可以以各种消费者子系统识别的格式传送分组数据，每个消费者子系统可以耦合 到分组处理电路。 分组处理电路可以被实现为半导体器件，并且可以允许封装的应用数据被路由到多个不同类型的应用接收器或处理器，形成点对点或多点串行或并行数据流 标准的传输涵盖了ISO数据通信栈的多个层次。
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公开(公告)号：US08190796B2
公开(公告)日：2012-05-29
申请号：US10979924
申请日：2004-11-02
申请人： Neil Winchester , William Chiechi , Paul Brant
发明人： Neil Winchester , William Chiechi , Paul Brant
CPC分类号： G06F13/28
摘要： A memory alignment system for efficient data transfer between a local memory that is configured in a host system, and a remote memory, comprises a data communications controller configured in the host system to align transmitted and received data based on formatting information received from the host system. When transmitting data from local system memory, for example over an Ethernet connection, communications control driver software may first write formatting information corresponding to the data into the data communications controller. The data communications controller is operable to align the data based on the formatting information as the driver software moves the data into a configurable transmit data buffer inside the data communications controller. Similarly, the driver software may write formatting information for receive data into a receive-format configuration buffer. The data communications controller may align the receive data based on the receive-formatting information as the receive data is being read by the host system. Because the data communications controller performs all the required data alignment, no data alignment by the host processor is required.
摘要翻译： 用于在配置在主机系统中的本地存储器与远程存储器之间进行有效数据传输的存储器对准系统包括配置在主机系统中的数据通信控制器，用于根据从主机系统接收的格式化信息对准发送和接收的数据 。 当从本地系统存储器发送数据时，例如通过以太网连接，通信控制驱动器软件可以首先将对应于数据的格式化信息写入数据通信控制器。 当驱动器软件将数据移动到数据通信控制器内的可配置发送数据缓冲器中时，数据通信控制器可操作以基于格式化信息对准数据。 类似地，驱动软件可以将用于接收数据的格式化信息写入接收格式配置缓冲器。 当主机系统正在读取接收数据时，数据通信控制器可以基于接收格式化信息对准接收数据。 由于数据通信控制器执行所有必需的数据对齐，因此不需要主机处理器进行数据对齐。
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