公开(公告)号：US20100206748A1

公开(公告)日：2010-08-19

申请号：US12670531

申请日：2008-07-31

Applicant: Mitsuhiro Morita ,  Toshiaki Baba ,  Hiroshi Yoshida ,  Emi Nishimura

Inventor： Mitsuhiro Morita ,  Toshiaki Baba ,  Hiroshi Yoshida ,  Emi Nishimura

IPC: G01N27/327

CPC classification number: G01N27/3273 ,  A61B10/0051 ,  C12Q1/005

Abstract: Provided is a stress measurement kit that is economical and that has good sensitivity. The stress measurement kit for measuring a stress level of a test subject includes: (A) a sensor chip including an electrically insulating substrate, and an electrode system that is placed on the electrically insulating substrate and that includes at least a working electrode and a counter electrode, wherein glucose dehydrogenase (GDH) and an electron mediator are immobilized on the working electrode; (B) a polysaccharide; and (C) a sensor body including an insertion hole into which the sensor chip is inserted, an electrical measurement means that is electrically connected to the electrode system of the sensor chip in a state where the sensor chip is inserted into the insertion hole, and a conversion means by which a current value or an electric quantity measured by the electrical measurement means is converted into an amylase activity value.

Abstract translation: 提供了一种经济且具有良好灵敏度的应力测量套件。 用于测量受检对象的应力水平的应力测量套件包括：（A）包括电绝缘衬底的传感器芯片和放置在电绝缘衬底上并且至少包括工作电极和计数器的电极系统 电极，其中葡萄糖脱氢酶（GDH）和电子介体固定在工作电极上; （B）多糖; 和（C）传感器本体，其包括插入有传感器芯片的插入孔，在传感器芯片插入插入孔的状态下电连接到传感器芯片的电极系统的电测量装置，以及 将通过电测量装置测量的电流值或电量转换成淀粉酶活性值的转换装置。

公开(公告)号：US07755157B2

公开(公告)日：2010-07-13

申请号：US11389171

申请日：2006-03-27

Applicant: Toshio Asaumi ,  Toshiaki Baba ,  Akira Terakawa ,  Yasufumi Tsunomura

Inventor： Toshio Asaumi ,  Toshiaki Baba ,  Akira Terakawa ,  Yasufumi Tsunomura

IPC: H01L31/105

CPC classification number: B82Y20/00 ,  H01L31/035245 ,  H01L31/0747 ,  H01L31/075 ,  H01L31/202 ,  Y02E10/548 ,  Y02P70/521

Abstract: Solar cells and methods of their manufacture are described that exhibit decreased or eliminated leak current, improved open voltage and improved fill factor characteristics. In an embodiment, a separate processed surface is interposed between a first and a second main surface of a crystal substrate, as prepared by laser irradiation and cut processing. The laser irradiation is applied to an amorphous semiconductor layer of the same conductive type as an underlying single crystal substrate, but does not penetrate an underlying amorphous opposite type layer. Details of lamination and laser characteristics for processing the layers are provided.

Abstract translation: 描述了太阳能电池及其制造方法，其表现出减少或消除的泄漏电流，改善的开路电压和改善的填充因子特性。 在一个实施例中，通过激光照射和切割处理制备的单独的经处理的表面插入在晶体基板的第一和第二主表面之间。 激光照射被施加到与下面的单晶衬底相同的导电类型的非晶半导体层，但不会穿透下面的非晶相对型层。 提供用于处理层的层压和激光特性的细节。

公开(公告)号：US07712002B2

公开(公告)日：2010-05-04

申请号：US11592163

申请日：2006-11-03

Applicant: Toshiaki Baba

Inventor： Toshiaki Baba

IPC: G01R31/28

CPC classification number: G01R31/318594

Abstract: The present invention provides a test circuit for a semiconductor integrated circuit that can be used for testing plural of logic blocks each having plural input-output terminals. This test circuit is provided with scanning flip-flop (SFF) circuits whose output terminals are connected to the input terminals of the logic blocks. The SFF circuits hold test data which is sequentially supplied, supply the test data to the logic blocks and receive logic operation data generated from the logic blocks. The logic operation data may be sequentially supplied from the SFF circuits, on the basis of which performances of the logic blocks are examined.

Abstract translation: 本发明提供一种用于半导体集成电路的测试电路，其可用于测试多个具有多个输入 - 输出端子的逻辑块。 该测试电路设有扫描触发器（SFF）电路，其输出端连接到逻辑块的输入端。 SFF电路保存顺序提供的测试数据，将测试数据提供给逻辑块，并接收从逻辑块生成的逻辑运算数据。 逻辑运算数据可以从SFF电路依次检查逻辑块的性能来依次提供。

公开(公告)号：US07214872B2

公开(公告)日：2007-05-08

申请号：US10245087

申请日：2002-09-17

Applicant: Eiji Maruyama ,  Toshiaki Baba

Inventor： Eiji Maruyama ,  Toshiaki Baba

IPC: H01L31/00

CPC classification number: H01L31/022475

Abstract: An ITO film as a transparent conductive film is formed on a semiconductor layer comprising an amorphous semiconductor or a microcrystalline semiconductor, a comb-like collecting electrode is formed on the ITO film, and a cover glass containing alkaline ions is placed on the ITO film and collecting electrode with a resin film made of EVA between them. The (222) plane orientation degree of the ITO film (transparent conductive film) is not less than 1.0, preferably not less than 1.2 and not more than 2.6, and more preferably not less than 1.4 and not more than 2.5. Alternatively, the transparent conductive film has an orientation of (321) planes on the boundary side with respect to the semiconductor layer and mainly an orientation of (222) planes in the remaining portion. When the total thickness of the ITO film is 100 nm, the (321)/(222) diffraction strength ratio in a 10 nm-thick portion on the semiconductor layer side is not less than 0.5 and not more than 2.5.

Abstract translation: 在包括非晶半导体或微晶半导体的半导体层上形成作为透明导电膜的ITO膜，在ITO膜上形成梳状收集电极，将含有碱离子的覆盖玻璃放置在ITO膜上， 在它们之间用EVA制成的树脂膜收集电极。 ITO膜（透明导电膜）的（222）面取向度为1.0以上，优选为1.2以上且2.6以下，更优选为1.4以上且2.5以下。 或者，透明导电膜在边界侧相对于半导体层具有取向（321）面，主要在其余部分具有（222）面的取向。 当ITO膜的总厚度为100nm时，半导体层侧的10nm厚的部分的（321）/（222）衍射强度比不小于0.5且不大于2.5。

公开(公告)号：US20060219292A1

公开(公告)日：2006-10-05

申请号：US11389171

申请日：2006-03-27

Applicant: Toshio Asaumi ,  Toshiaki Baba ,  Akira Terakawa ,  Yasufumi Tsunomura

Inventor： Toshio Asaumi ,  Toshiaki Baba ,  Akira Terakawa ,  Yasufumi Tsunomura

IPC: H01L31/00

CPC classification number: B82Y20/00 ,  H01L31/035245 ,  H01L31/0747 ,  H01L31/075 ,  H01L31/202 ,  Y02E10/548 ,  Y02P70/521

Abstract: Solar cells and methods of their manufacture are described that exhibit decreased or eliminated leak current, improved open voltage and improved fill factor characteristics. In an embodiment, a separate processed surface is interposed between a first and a second main surface of a crystal substrate, as prepared by laser irradiation and cut processing. The laser irradiation is applied to an amorphous semiconductor layer of the same conductive type as an underlying single crystal substrate, but does not penetrate an underlying amorphous opposite type layer. Details of lamination and laser characteristics for processing the layers are provided.

Abstract translation: 描述了太阳能电池及其制造方法，其表现出减少或消除的泄漏电流，改善的开路电压和改善的填充因子特性。 在一个实施例中，通过激光照射和切割处理制备的单独的经处理的表面插入晶体基板的第一和第二主表面之间。 激光照射被施加到与下面的单晶衬底相同的导电类型的非晶半导体层，但不会穿透下面的非晶相对型层。 提供了用于处理层的层压和激光特性的细节。

公开(公告)号：US06609240B2

公开(公告)日：2003-08-19

申请号：US09984839

申请日：2001-10-31

Applicant: Toshiaki Baba

Inventor： Toshiaki Baba

IPC: G06F1750

CPC classification number: G06F17/5068

Abstract: There is provided a method of designing a conductive pattern layout between a plurality of blocks in an LSI, the conductive pattern transferring data from one block to the other blocks, comprising: (a) extracting the blocks from logic circuit data; (b) preparing a floor plan which defines a provisional arrangement of the blocks; (c) arranging a plurality of conductive pattern cells between the plurality of blocks after preparing the floor plan; (d) re-arranging the blocks on the basis of the arrangement of the conductive pattern cells; (e) arranging a plurality of power source patterns; and (g) arranging a plurality of signal patterns. Due to this conductive pattern layout and method of designing thereof, wiring between blocks can be carried out simply and with high accuracy.

Abstract translation: 提供了一种在LSI中的多个块之间设计导电图案布局的方法，所述导电图案将数据从一个块传送到其他块，包括：（a）从逻辑电路数据中提取块; （b）制定一项界定一个临时安排的楼层平面图; （c）在准备所述平面图之后，在所述多个块之间布置多个导电图案单元; （d）基于导电图案单元的布置重新布置块; （e）布置多个电源图案; 和（g）排列多个信号图形。 由于该导电图案布局及其设计方法，可以简单且高精度地执行块之间的布线。

公开(公告)号：US20130186456A1

公开(公告)日：2013-07-25

申请号：US13557255

申请日：2012-07-25

Applicant: Daisuke IDE ,  Takahiro MISHIMA ,  Masato SHIGEMATSU ,  Toshiaki BABA ,  Hiroyuki MORI ,  Mitsuaki MORIGAMI ,  Yuji HISHIDA ,  Hitoshi SAKATA ,  Ryo GOTO

Inventor： Daisuke IDE ,  Takahiro MISHIMA ,  Masato SHIGEMATSU ,  Toshiaki BABA ,  Hiroyuki MORI ,  Mitsuaki MORIGAMI ,  Yuji HISHIDA ,  Hitoshi SAKATA ,  Ryo GOTO

IPC: H01L31/0352 ,  H01L31/18 ,  H01L31/078

CPC classification number: H01L31/035281 ,  H01L31/022441 ,  H01L31/03529 ,  H01L31/0747 ,  H01L31/078 ,  H01L31/1804 ,  H01L31/1884 ,  Y02E10/547 ,  Y02P70/521

Abstract: An aspect of the invention provides a solar cell that comprises a semiconductor substrate having a light-receiving surface and a rear surface; a first semiconductor layer having a first conductivity type; a second semiconductor layer having a second conductivity type, the first semiconductor layer and the second semiconductor layer being formed on the rear surface, and a trench formed in the rear surface, wherein the first semiconductor layer is formed on the rear surface in which the trench is not formed, and the second semiconductor layer is formed on a side surface of the trench in an arrangement direction in which the first semiconductor layer and the second semiconductor layer are alternately arranged and on a bottom surface of the trench.

Abstract translation: 本发明的一个方面提供了一种太阳能电池，其包括具有光接收表面和后表面的半导体衬底; 具有第一导电类型的第一半导体层; 具有第二导电类型的第二半导体层，在后表面上形成第一半导体层和第二半导体层，以及形成在后表面中的沟槽，其中第一半导体层形成在沟槽的后表面上 并且所述第二半导体层在所述沟槽的侧表面上沿所述第一半导体层和所述第二半导体层交替布置的排列方向形成在所述沟槽的底表面上。

公开(公告)号：US20070143652A1

公开(公告)日：2007-06-21

申请号：US11592163

申请日：2006-11-03

Applicant: Toshiaki Baba

Inventor： Toshiaki Baba

IPC: G01R31/28

CPC classification number: G01R31/318594

Abstract: The present invention provides a test circuit for a semiconductor integrated circuit that can be used for testing plural of logic blocks each having plural input-output terminals. This test circuit is provided with scanning flip-flop (SFF) circuits whose output terminals are connected to the input terminals of the logic blocks. The SFF circuits hold test data which is sequentially supplied, supply the test data to the logic blocks and receive logic operation data generated from the logic blocks. The logic operation data may be sequentially supplied from the SFF circuits, on the basis of which performances of the logic blocks are examined.

Abstract translation: 本发明提供一种用于半导体集成电路的测试电路，其可用于测试多个具有多个输入 - 输出端子的逻辑块。 该测试电路设有扫描触发器（SFF）电路，其输出端连接到逻辑块的输入端。 SFF电路保存顺序提供的测试数据，将测试数据提供给逻辑块，并接收从逻辑块生成的逻辑运算数据。 逻辑运算数据可以从SFF电路依次检查逻辑块的性能来依次提供。

公开(公告)号：US10181540B2

公开(公告)日：2019-01-15

申请号：US13557255

申请日：2012-07-25

Applicant: Daisuke Ide ,  Takahiro Mishima ,  Masato Shigematsu ,  Toshiaki Baba ,  Hiroyuki Mori ,  Mitsuaki Morigami ,  Yuji Hishida ,  Hitoshi Sakata ,  Ryo Goto

Inventor： Daisuke Ide ,  Takahiro Mishima ,  Masato Shigematsu ,  Toshiaki Baba ,  Hiroyuki Mori ,  Mitsuaki Morigami ,  Yuji Hishida ,  Hitoshi Sakata ,  Ryo Goto

IPC: H01L31/18 ,  H01L31/078 ,  H01L31/0224 ,  H01L31/0352 ,  H01L31/0747

Abstract: An aspect of the invention provides a solar cell that comprises a semiconductor substrate having a light-receiving surface and a rear surface; a first semiconductor layer having a first conductivity type; a second semiconductor layer having a second conductivity type, the first semiconductor layer and the second semiconductor layer being formed on the rear surface, and a trench formed in the rear surface, wherein the first semiconductor layer is formed on the rear surface in which the trench is not formed, and the second semiconductor layer is formed on a side surface of the trench in an arrangement direction in which the first semiconductor layer and the second semiconductor layer are alternately arranged and on a bottom surface of the trench.

公开(公告)号：US09159859B2

公开(公告)日：2015-10-13

申请号：US12375768

申请日：2007-07-31

Applicant: Toshiaki Baba

Inventor： Toshiaki Baba

IPC: H01L31/00 ,  H01L31/05 ,  H01L31/0224 ,  H01L31/042 ,  H01L31/02

CPC classification number: H01L31/0504 ,  H01L31/02013 ,  H01L31/042 ,  Y02E10/50

Abstract: Disclosed is a solar cell module including: a plurality of solar cell units each including a supporting substrate 30 and an even number of solar cells 20 disposed on the supporting substrate 30; and a conductor 10 configured to electrically connecting surfaces of adjacent solar cells 20 that have opposite surface polarities and are formed in respective solar cell units adjacent to each other. The solar cells 20 having the opposite surface polarities are alternately arranged in each of the solar cell units so that the surface polarities of the adjacent solar cells 20 are opposite to each other, and the solar cell unit has one or more sets of two solar cells electrically connected to each other on the supporting substrate 30.

Abstract translation: 公开了一种太阳能电池模块，包括：多个太阳能电池单元，每个太阳能电池单元包括支撑基板30和设置在支撑基板30上的偶数个太阳能电池20; 以及导体10，被配置为将相邻的太阳能电池20的表面极性电连接并形成在彼此相邻的各个太阳能电池单元中。 具有相反表面极性的太阳能电池20交替地布置在每个太阳能电池单元中，使得相邻的太阳能电池20的表面极性彼此相反，并且太阳能电池单元具有一组或多组两个太阳能电池 在支撑基板30上彼此电连接。