公开(公告)号：US07302027B2

公开(公告)日：2007-11-27

申请号：US10356236

申请日：2003-01-31

申请人： David Zhang ,  Timothy S. Fu

发明人： David Zhang ,  Timothy S. Fu

IPC分类号： H04L7/00

CPC分类号： G06F5/08

摘要： A system and method for distributing data in a system. The system comprises a control register logic circuits located at scattered locations in the system, where a location is defined as scattered if the propagation delay of data sent from the control register is more than approximately one clock period. The system also comprises one or more shift registers coupled to the control register and the logic circuits. A section of each shift register is placed in proximity to each logic circuit and data is shifted serially from the control register through the shift registers to the logic circuits. A synchronizer circuit is coupled to the shift registers to synchronize data arriving at each section of the shift registers with a shift control signal arriving at the same section of the shift register.

摘要翻译： 用于在系统中分发数据的系统和方法。 该系统包括位于系统中分散位置的控制寄存器逻辑电路，其中如果从控制寄存器发送的数据的传播延迟大于大约一个时钟周期，那么位置被定义为分散的。 该系统还包括耦合到控制寄存器和逻辑电路的一个或多个移位寄存器。 每个移位寄存器的一部分放置在每个逻辑电路附近，并且数据从控制寄存器通过移位寄存器串行移位到逻辑电路。 同步器电路耦合到移位寄存器，以将到达移位寄存器的每个部分的数据与到达移位寄存器的相同部分的移位控制信号同步。

公开(公告)号：US5111464A

公开(公告)日：1992-05-05

申请号：US444639

申请日：1989-12-01

申请人： Paul M. Farmwald ,  Timothy S. Fu

发明人： Paul M. Farmwald ,  Timothy S. Fu

IPC分类号： G06F12/16 ,  G06F11/07 ,  G06F11/10 ,  G06F11/30

CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/1048

摘要： Error reporting circuitry interrupts the CPU on the occurrence of a single bit memory error only when the chip member causing the error is different from the chip number that caused the previous error.