公开(公告)号：US4734909A

公开(公告)日：1988-03-29

申请号：US898810

申请日：1986-08-21

Applicant: Donald B. Bennett ,  Lee T. Thorsrud ,  Thomas W. Petschauer

Inventor： Donald B. Bennett ,  Lee T. Thorsrud ,  Thomas W. Petschauer

IPC: F02B75/02 ,  G06F11/00 ,  G06F11/10 ,  G06F13/374 ,  G06F13/42 ,  H04J3/02

CPC classification number: G06F13/4217 ,  G06F11/0751 ,  G06F11/10 ,  G06F13/374 ,  F02B2075/025

Abstract: A bus arbitration system comprising a plurality of bus lines and a clock which produces first and second phrases in which a drive generates a first logic state during the first phase to precharge the capacitance associated with the bus lines and generates either first or second logic state during the second phase. Also, a bus interface is described in which different types of information are transmitted during different phases.

Abstract translation: 一种总线仲裁系统，包括多个总线和产生第一和第二短语的时钟，其中驱动器在第一阶段期间产生第一逻辑状态以对与总线线路相关联的电容进行预充电，并且在第一和第二短语期间产生第一或第二逻辑状态 第二阶段 此外，描述了在不同阶段期间传送不同类型的信息的总线接口。

公开(公告)号：US4500988A

公开(公告)日：1985-02-19

申请号：US355803

申请日：1982-03-08

Applicant: Donald B. Bennett ,  Lee T. Thorsrud ,  Thomas W. Petschauer

Inventor： Donald B. Bennett ,  Lee T. Thorsrud ,  Thomas W. Petschauer

IPC: G06F13/40 ,  H03K19/0948 ,  H04L5/16 ,  H04L12/40 ,  H03K17/00

CPC classification number: H04L5/16 ,  G06F13/4072 ,  H03K19/0948

Abstract: Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical "0", or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical "1". Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines.

Abstract translation: VLSI有线或驱动程序支持高性能同步（25 MHz线路传输速率）并行数字通信总线上的双向通信，该数字通信总线通过大规模集成（VLSI）电路设备互连大量（高达1米总线） 接收器（D / R）电路元件在用于总线驱动的两相总线电气协议下协同工作。 在大约10纳秒的第一阶段期间，所有接口驱动器电路将连接的总线线路加上驱动或上拉至+3V.d.c. 逻辑高条件。 在每个40纳秒周期时间期间，在大约20纳秒的第二阶段，D / R电路呈现高阻抗到充电总线，用于维持这样的逻辑高和逻辑“0”的传输，或者一个或多个D / R电路耗尽 线电压朝向0 vdc 用于传输逻辑“1”。 总线线路支持两路驱动器到接收机，有线或广播和/或窃听通信。

公开(公告)号：US4825438A

公开(公告)日：1989-04-25

申请号：US98634

申请日：1987-11-16

Applicant: Donald B. Bennett ,  Lee T. Thorsrud ,  Thomas W. Petschauer

Inventor： Donald B. Bennett ,  Lee T. Thorsrud ,  Thomas W. Petschauer

IPC: F02B75/02 ,  G06F11/00 ,  G06F11/10 ,  G06F13/374 ,  G06F13/42

CPC classification number: G06F13/4217 ,  G06F11/0751 ,  G06F11/10 ,  G06F13/374 ,  F02B2075/025

Abstract: A bus error detection system is used to detect binary bus error signals. The bus lines include an odd parity line and an even parity line. A clock means provides at least two clock signal phases. An activatable driver drives both of the odd and the even parity lines to the same predefined logic level each time a first clock signal phase occurs. A parity checker coupled to the drive checks during a second clock signal phase the parity of the binary signals which appeared on said bus lines during a preceding first clock signal phase. The driver then drives either the odd or the even parity lines to a predefined logic state according to the parity determined by the parity checker during the second clock signal phase. A verification circuit verifies that only one of the odd and the even parity lines has been driven to a predefined logic state during said second clock phase, and that of both the odd and the even parity lines have been driven during said first clock signal phase to the same predefined logic level.

Abstract translation: 总线误差检测系统用于检测二进制总线误差信号。 总线包括奇校验线和偶校验线。 时钟装置提供至少两个时钟信号相位。 每次发生第一时钟信号相位时，可激活的驱动器将奇偶校验线驱动到相同的预定逻辑电平。 耦合到驱动器的奇偶校验器在第二时钟信号期间检查在前一个第一时钟信号相位期间在所述总线上出现的二进制信号的奇偶校验。 然后，驱动器根据在第二时钟信号相位期间由奇偶校验器确定的奇偶校验，将奇数或偶校验线驱动到预定逻辑状态。 验证电路验证在所述第二时钟相位期间奇偶校验线中仅一个已经被驱动到预定义的逻辑状态，并且在所述第一时钟信号相位期间已经驱动奇偶校验线的奇数和偶校验线的一个到 相同的预定义逻辑电平。