公开(公告)号：US08156050B2

公开(公告)日：2012-04-10

申请号：US12471701

申请日：2009-05-26

申请人： Roger L. Correll ,  Steven D. Lawyer ,  Thomas R. O'Brien ,  James W. Evans, II ,  M. Denise Wittmer ,  Karen B. Hixson

发明人： Roger L. Correll ,  Steven D. Lawyer ,  Thomas R. O'Brien ,  James W. Evans, II ,  M. Denise Wittmer ,  Karen B. Hixson

IPC分类号： G06F17/50 ,  G06F9/44

CPC分类号： G06Q10/06 ,  G06Q10/0631 ,  G06Q10/06313 ,  G06Q10/06316 ,  G06Q10/0633 ,  G06Q10/0635 ,  G06Q10/0637 ,  G06Q50/188

摘要： A project management system comprising a first, second, third, fourth and fifth processing sequences embodied in a computer readable medium. The first processing sequence is operable to provide a user interface to display a plurality of alert indicia corresponding to a plurality of alert status of a plurality of project requirements. The second processing sequence is operable to convert an incomplete requirement to a complete requirement upon completion of a task corresponding to the incomplete requirement. The third processing sequence is operable to determine the alert status of the requirements of the plurality of projects based on a time difference between a current date and a target date corresponding to each requirement. The fourth and fifth processing sequences are operable override the alert status based on user selections.

摘要翻译： 一种项目管理系统，包括体现在计算机可读介质中的第一，第二，第三，第四和第五处理序列。 第一处理顺序可操作以提供用户界面来显示与多个项目要求的多个警报状态相对应的多个警报标记。 第二处理顺序可操作以在完成与不完整要求相对应的任务完成时将不完整要求转换为完整要求。 第三处理顺序可操作以基于当前日期与对应于每个需求的目标日期之间的时间差来确定多个项目的要求的警报状态。 第四和第五处理序列可操作地基于用户选择覆盖警报状态。

公开(公告)号：US07853901B2

公开(公告)日：2010-12-14

申请号：US12109501

申请日：2008-04-25

申请人： Viswanathan Lakshmanan ,  Thomas R. O'Brien ,  Richard D. Blinne

发明人： Viswanathan Lakshmanan ,  Thomas R. O'Brien ,  Richard D. Blinne

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

摘要翻译： 一种用于生产数字集成电路设计系列的方法，其中家族具有最高级别的设计和至少一个较低级别的设计。 最高水平的设计是首次生产。 然后，在没有用户干预的编程计算系统中，自动处理最高级别的设计以选择性地移除至少一个预定的金属层。 至少一个去除的金属层的最近的剩余覆盖层被自动映射到至少一个移除的金属层的最接近的剩余的下层，由此产生至少一个较低级设计。

公开(公告)号：US20100306011A1

公开(公告)日：2010-12-02

申请号：US12623374

申请日：2009-11-21

申请人： Roger L. Correll ,  Steven D. Lawyer ,  Thomas R. O'Brien ,  James W. Evans, II ,  M. Denise Wittmer ,  Karen B. Hixson

发明人： Roger L. Correll ,  Steven D. Lawyer ,  Thomas R. O'Brien ,  James W. Evans, II ,  M. Denise Wittmer ,  Karen B. Hixson

IPC分类号： G06Q10/00 ,  G06F17/30 ,  G06F3/048

CPC分类号： G06Q10/06 ,  G06Q10/0631 ,  G06Q10/06313 ,  G06Q10/06316 ,  G06Q10/0633 ,  G06Q10/0635 ,  G06Q10/0637 ,  G06Q50/188

摘要： A project management system comprising a first, second, third, fourth and fifth processing sequences embodied in a computer readable medium. The first processing sequence is operable to provide a user interface to display a plurality of alert indicia corresponding to a plurality of alert status of a plurality of project requirements. The second processing sequence is operable to convert an incomplete requirement to a complete requirement upon completion of a task corresponding to the incomplete requirement. The third processing sequence is operable to determine the alert status of the requirements of the plurality of projects based on a time difference between a current date and a target date corresponding to each requirement. The fourth and fifth processing sequences are operable override the alert status based on user selections.

摘要翻译： 一种项目管理系统，包括体现在计算机可读介质中的第一，第二，第三，第四和第五处理序列。 第一处理顺序可操作以提供用户界面来显示对应于多个项目要求的多个警报状态的多个警报标记。 第二处理顺序可操作以在完成与不完整要求相对应的任务完成时将不完整要求转换为完整要求。 第三处理顺序可操作以基于当前日期与对应于每个需求的目标日期之间的时间差来确定多个项目的要求的警报状态。 第四和第五处理序列可操作地基于用户选择覆盖警报状态。

公开(公告)号：US20090271755A1

公开(公告)日：2009-10-29

申请号：US12109501

申请日：2008-04-25

申请人： Viswanathan Lakshmanan ,  Thomas R. O'Brien ,  Richard D. Blinne

发明人： Viswanathan Lakshmanan ,  Thomas R. O'Brien ,  Richard D. Blinne

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

摘要翻译： 一种用于生产数字集成电路设计系列的方法，其中家族具有最高级别的设计和至少一个较低级别的设计。 最高水平的设计是首次生产。 然后，在没有用户干预的编程计算系统中，自动处理最高级别的设计以选择性地移除至少一个预定的金属层。 至少一个去除的金属层的最近的剩余覆盖层被自动映射到至少一个移除的金属层的最接近的剩余的下层，由此产生至少一个较低级设计。

公开(公告)号：US20090051006A1

公开(公告)日：2009-02-26

申请号：US11843768

申请日：2007-08-23

申请人： Richard T. Schultz ,  Thomas R. O'Brien ,  Viswanathan Lakshmanan ,  David M. Ratchkov ,  Stefan G. Block

发明人： Richard T. Schultz ,  Thomas R. O'Brien ,  Viswanathan Lakshmanan ,  David M. Ratchkov ,  Stefan G. Block

IPC分类号： H01G4/40

CPC分类号： H01G4/40

摘要： A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.

摘要翻译： 设置在第一轨道和第二轨道之间的去耦电路，其中第三电力轨设置在第一和第二轨道之间。 具有第一电极和第二电极的电阻器设置在第一和第二导轨之间。 两个电容器设置在第一和第二导轨之间。 电阻器连接到第三导轨和两个电容器。 以这种方式，两个电容器相对于电阻器串联连接，并且彼此并联。 两个电容器中的第一个连接到第一导轨，并且两个电容器中的第二个连接到第二导轨。 电阻器和两个电容器中的至少一个至少部分地设置在第三导轨下方。

公开(公告)号：US07392496B1

公开(公告)日：2008-06-24

申请号：US11538187

申请日：2006-10-03

申请人： Richard T. Schultz ,  Thomas R. O'Brien

发明人： Richard T. Schultz ,  Thomas R. O'Brien

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A method and firmware for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit includes steps of receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer, finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information, identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer, calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire, and generating as output at least one of the wire width and the fracture interval for the dummy metal wire.

摘要翻译： 一种用于避免由集成电路的回填金属层中的工艺缺陷引起的定时违规的方法和固件包括以下步骤：接收用于集成电路设计的输入定时信息，该集成电路设计包括至少一个金属层和多条信号线以及虚设金属线 在金属层中，从定时信息中找出金属层中的每个信号线的建立时间和保持时间中的至少一个，从建立时间和保持时间的至少一个识别时序关键信号线， 当信号线通过金属层中的工艺缺陷而短路到虚设金属线时，在信号线中将产生定时违规的信号线中的一条，计算线宽度，断裂间隔和 间隔，用于修改虚拟金属线，以避免在时间关键信号线中的定时违反，并且产生作为输出的线宽度和断裂间隔中的至少一个 虚拟金属线。

公开(公告)号：US10037498B2

公开(公告)日：2018-07-31

申请号：US12623374

申请日：2009-11-21

申请人： Roger L. Correll ,  Steven D. Lawyer ,  Thomas R. O'Brien ,  James W. Evans, II ,  M. Denise Wittmer ,  Karen B. Hixson

发明人： Roger L. Correll ,  Steven D. Lawyer ,  Thomas R. O'Brien ,  James W. Evans, II ,  M. Denise Wittmer ,  Karen B. Hixson

IPC分类号： G06Q10/06 ,  G06Q50/18

CPC分类号： G06Q10/06 ,  G06Q10/0631 ,  G06Q10/06313 ,  G06Q10/06316 ,  G06Q10/0633 ,  G06Q10/0635 ,  G06Q10/0637 ,  G06Q50/188

摘要： A project management system comprising a first, second, third, fourth and fifth processing sequences embodied in a computer readable medium. The first processing sequence is operable to provide a user interface to display a plurality of alert indicia corresponding to a plurality of alert status of a plurality of project requirements. The second processing sequence is operable to convert an incomplete requirement to a complete requirement upon completion of a task corresponding to the incomplete requirement. The third processing sequence is operable to determine the alert status of the requirements of the plurality of projects based on a time difference between a current date and a target date corresponding to each requirement. The fourth and fifth processing sequences are operable override the alert status based on user selections.

公开(公告)号：US20100305987A1

公开(公告)日：2010-12-02

申请号：US12471701

申请日：2009-05-26

申请人： Roger L. Correll ,  Steven D. Lawyer ,  Thomas R. O'Brien ,  James W. Evans, II ,  M. Denise Wittmer ,  Karen B. Hixson

发明人： Roger L. Correll ,  Steven D. Lawyer ,  Thomas R. O'Brien ,  James W. Evans, II ,  M. Denise Wittmer ,  Karen B. Hixson

IPC分类号： G06Q10/00

CPC分类号： G06Q10/06 ,  G06Q10/0631 ,  G06Q10/06313 ,  G06Q10/06316 ,  G06Q10/0633 ,  G06Q10/0635 ,  G06Q10/0637 ,  G06Q50/188

摘要： A project management system comprising a first, second, third, fourth and fifth processing sequences embodied in a computer readable medium. The first processing sequence is operable to provide a user interface to display a plurality of alert indicia corresponding to a plurality of alert status of a plurality of project requirements. The second processing sequence is operable to convert an incomplete requirement to a complete requirement upon completion of a task corresponding to the incomplete requirement. The third processing sequence is operable to determine the alert status of the requirements of the plurality of projects based on a time difference between a current date and a target date corresponding to each requirement. The fourth and fifth processing sequences are operable override the alert status based on user selections.

摘要翻译： 一种项目管理系统，包括体现在计算机可读介质中的第一，第二，第三，第四和第五处理序列。 第一处理顺序可操作以提供用户界面来显示对应于多个项目要求的多个警报状态的多个警报标记。 第二处理顺序可操作以在完成与不完整要求相对应的任务完成时将不完整要求转换为完整要求。 第三处理顺序可操作以基于当前日期与对应于每个需求的目标日期之间的时间差来确定多个项目的要求的警报状态。 第四和第五处理序列可操作地基于用户选择覆盖警报状态。

公开(公告)号：US07829973B2

公开(公告)日：2010-11-09

申请号：US11843768

申请日：2007-08-23

申请人： Richard T. Schultz ,  Thomas R. O'Brien ,  Viswanathan Lakshmanan ,  David M. Ratchkov ,  Stefan G. Block

发明人： Richard T. Schultz ,  Thomas R. O'Brien ,  Viswanathan Lakshmanan ,  David M. Ratchkov ,  Stefan G. Block

IPC分类号： H01G4/40

CPC分类号： H01G4/40

摘要： A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.

摘要翻译： 设置在第一轨道和第二轨道之间的去耦电路，其中第三电力轨设置在第一和第二轨道之间。 具有第一电极和第二电极的电阻器设置在第一和第二导轨之间。 两个电容器设置在第一和第二导轨之间。 电阻器连接到第三导轨和两个电容器。 以这种方式，两个电容器相对于电阻器串联连接，并且彼此并联。 两个电容器中的第一个连接到第一导轨，并且两个电容器中的第二个连接到第二导轨。 电阻器和两个电容器中的至少一个至少部分地设置在第三导轨下方。

公开(公告)号：US20080155488A1

公开(公告)日：2008-06-26

申请号：US11538187

申请日：2006-10-03

申请人： RICHARD T. SCHULTZ ,  Thomas R. O'Brien

发明人： RICHARD T. SCHULTZ ,  Thomas R. O'Brien

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A method and firmware for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit includes steps of receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer, finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information, identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer, calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire, and generating as output at least one of the wire width and the fracture interval for the dummy metal wire.

摘要翻译： 一种用于避免由集成电路的回填金属层中的工艺缺陷引起的定时违规的方法和固件包括以下步骤：接收用于集成电路设计的输入定时信息，该集成电路设计包括至少一个金属层和多条信号线以及虚设金属线 在金属层中，从定时信息中找出金属层中的每个信号线的建立时间和保持时间中的至少一个，从建立时间和保持时间的至少一个识别时序关键信号线， 当信号线通过金属层中的工艺缺陷而短路到虚设金属线时，在信号线中将产生定时违规的信号线中的一条，计算线宽度，断裂间隔和 间隔，用于修改虚拟金属线，以避免在时间关键信号线中的定时违反，并且产生作为输出的线宽度和断裂间隔中的至少一个 虚拟金属线。