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公开(公告)号:US07660257B2
公开(公告)日:2010-02-09
申请号:US11388479
申请日:2006-03-23
申请人: Takanori Yoshimatsu
发明人: Takanori Yoshimatsu
IPC分类号: G08C15/00
CPC分类号: H01L23/544 , G11C29/006 , G11C29/44 , G11C29/56008 , G11C2029/4402 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要: There is provided a semiconductor device comprising, a function unit portion including a circuit element, rank data presenting results of a rank-classification test on the circuit element, the rank-classification test being performed on the basis of a plurality of test criteria on wafer state, a non-volatile memory portion in which the rank data are stored, and a control portion reading out the rank data from the non-volatile memory portion, the control portion being used in a product test after packaging.
摘要翻译: 提供了一种半导体器件,包括:包括电路元件的功能单元部分,呈现电路元件上的等级分类测试结果的秩数据,基于晶片上的多个测试标准执行等级分类测试 状态,其中存储秩数据的非易失性存储器部分以及从非易失性存储器部分读出秩数据的控制部分,所述控制部分在包装后的产品测试中使用。
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公开(公告)号:US20070007521A1
公开(公告)日:2007-01-11
申请号:US11388479
申请日:2006-03-23
申请人: Takanori Yoshimatsu
发明人: Takanori Yoshimatsu
IPC分类号: H01L23/58
CPC分类号: H01L23/544 , G11C29/006 , G11C29/44 , G11C29/56008 , G11C2029/4402 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要: There is provided a semiconductor device comprising, a function unit portion including a circuit element, rank data presenting results of a rank-classification test on the circuit element, the rank-classification test being performed on the basis of a plurality of test criteria on wafer state, a non-volatile memory portion in which the rank data are stored, and a control portion reading out the rank data from the non-volatile memory portion, the control portion being used in a product test after packaging.
摘要翻译: 提供了一种半导体器件,包括:包括电路元件的功能单元部分,呈现电路元件上的等级分类测试结果的秩数据,基于晶片上的多个测试标准执行等级分类测试 状态,其中存储秩数据的非易失性存储器部分以及从非易失性存储器部分读出秩数据的控制部分,所述控制部分在包装后的产品测试中使用。
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公开(公告)号:US06985395B2
公开(公告)日:2006-01-10
申请号:US10884105
申请日:2004-07-01
IPC分类号: G11C7/00
CPC分类号: G11C29/44
摘要: A semiconductor memory device is disclosed, which includes a memory cell array including memory cells arranged in rows and columns, a word line, a bit line, a row decoder and a column decoder, a sense amplifier provided for each of the columns of the memory cell array, a write latch circuit configured to store externally input data and sets data of one row of the memory cell array in the sense amplifiers in test mode, a read latch circuit configured to store data of one row, which is read from the memory cell array and set in the sense amplifiers in test mode, a first comparison circuit configured to compare the data stored in the write latch circuit and the data stored in the read latch circuit, and a first comparison result register configured to store a comparison result of the first comparison circuit.
摘要翻译: 公开了一种半导体存储器件,其包括存储单元阵列,该存储单元阵列包括以行和列排列的存储单元,字线,位线,行解码器和列解码器,为存储器的每列提供的读出放大器 单元阵列,写锁存电路,被配置为存储外部输入数据,并以测试模式设置读出放大器中的一行存储单元阵列的数据;读锁存器电路,被配置为存储从存储器读取的一行数据 单元阵列,并且在测试模式下设置在读出放大器中,第一比较电路,被配置为将存储在写入锁存电路中的数据与存储在读取锁存电路中的数据进行比较;第一比较结果寄存器,被配置为存储比较结果 第一个比较电路。
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公开(公告)号:US20050068816A1
公开(公告)日:2005-03-31
申请号:US10884105
申请日:2004-07-01
IPC分类号: G11C29/12 , G11C11/401 , G11C29/04 , G11C29/44 , G11C7/00
CPC分类号: G11C29/44
摘要: A semiconductor memory device is disclosed, which comprises a memory cell array including memory cells arranged in rows and columns, a word line, a bit line, a row decoder and a column decoder, a sense amplifier provided for each of the columns of the memory cell array, a write latch circuit configured to store externally input data and sets data of one row of the memory cell array in the sense amplifiers in test mode, a read latch circuit configured to store data of one row, which is read from the memory cell array and set in the sense amplifiers in test mode, a first comparison circuit configured to compare the data stored in the write latch circuit and the data stored in the read latch circuit, and a first comparison result register configured to store a comparison result of the first comparison circuit.
摘要翻译: 公开了一种半导体存储器件,其包括存储单元阵列,该存储单元阵列包括以行和列排列的存储单元,字线,位线,行解码器和列解码器,为存储器的每列提供的读出放大器 单元阵列,写锁存电路,被配置为存储外部输入数据,并以测试模式设置读出放大器中的一行存储单元阵列的数据;读锁存器电路,被配置为存储从存储器读取的一行数据 单元阵列,并且在测试模式下设置在读出放大器中,第一比较电路,被配置为将存储在写入锁存电路中的数据与存储在读取锁存电路中的数据进行比较;第一比较结果寄存器,被配置为存储比较结果 第一个比较电路。
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