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    Integrated circuit having embedded differential clock tree
    6.
    发明授权
    Integrated circuit having embedded differential clock tree 有权
    集成电路具有嵌入式差分时钟树

    公开(公告)号：US07759973B1

    公开(公告)日：2010-07-20

    申请号：US12174502

    申请日：2008-07-16

    申请人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    发明人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    IPC分类号： H03K19/177

    CPC分类号： G06F1/10 ,  H03K5/15013 ,  H03K19/1774 ,  H03K19/17784 ,  H03K19/17796

    摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

    摘要翻译： 一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

    Data alignment and deskewing module
    7.
    发明授权
    Data alignment and deskewing module 有权
    数据对齐和脱斜模块

    公开(公告)号：US07551646B1

    公开(公告)日：2009-06-23

    申请号：US10938151

    申请日：2004-09-10

    申请人： Qi Zhang ,  Jason R. Bergendahl ,  Atul V. Ghia ,  Suresh M. Menon

    发明人： Qi Zhang ,  Jason R. Bergendahl ,  Atul V. Ghia ,  Suresh M. Menon

    IPC分类号： H04J3/06

    CPC分类号： H04J3/0629

    摘要： A data alignment and deskewing module includes a delay calibration unit, a data alignment and deskew unit, and a delay unit. The delay calibration unit is operably coupled to generate a reference signal based on a reference clock and a mirrored delay line output signal. The data alignment and deskew unit is operably coupled to determine a delay selection signal based on a delayed and deskewed representation of an input data stream and propagation delay of a line on which the input data stream is received. The delay unit is operably coupled to produce the delayed and deskewed representation of the input data stream based on the reference signal and the delay selection signal.

    摘要翻译： 数据对准和去歪斜模块包括延迟校准单元，数据对准和去歪斜单元以及延迟单元。 延迟校准单元可操作地耦合以基于参考时钟和镜像延迟线输出信号产生参考信号。 数据对准和去歪斜单元可操作地耦合以基于输入数据流的延迟和偏斜校正表示以及接收输入数据流的线的传播延迟来确定延迟选择信号。 延迟单元可操作地耦合以基于参考信号和延迟选择信号产生输入数据流的延迟和去歪斜表示。

    Programmable logic device having an embedded differential clock tree
    8.
    发明授权
    Programmable logic device having an embedded differential clock tree 有权
    具有嵌入式差分时钟树的可编程逻辑器件

    公开(公告)号：US07414430B2

    公开(公告)日：2008-08-19

    申请号：US11511647

    申请日：2006-08-29

    申请人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    发明人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    IPC分类号： H03K19/177

    CPC分类号： G06F1/10 ,  H03K5/15013 ,  H03K19/1774 ,  H03K19/17784 ,  H03K19/17796

    摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

    摘要翻译： 一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。