公开(公告)号：US07428722B2

公开(公告)日：2008-09-23

申请号：US12007705

申请日：2008-01-15

申请人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

发明人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

IPC分类号： H03K19/00

CPC分类号： H03K19/1737

摘要： Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.

公开(公告)号：US20060164120A1

公开(公告)日：2006-07-27

申请号：US11044386

申请日：2005-01-27

申请人： Hare Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

发明人： Hare Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.

摘要翻译： 公开了一种使用输入逻辑路由单元（ILRC）多路复用器和输出逻辑路由单元（OLRC）多路复用器进行专用逻辑单元之间的本地连接的可编程逻辑结构。 在简单的可编程逻辑结构中，专用逻辑单元（DLC）以包括用于端口A的多个ILRC多路复用器和用于端口B的多个OLRC多路复用器的可编程逻辑结构实现。在多级可编程逻辑结构中，多列专用逻辑 单元被设计成具有彼此相邻的专用本地单元的列，其中每个DLC列用于实现特定的逻辑功能。 在第一实施例中，可以在专用逻辑单元之间进行本地连接。 在L级的第一个DLC中的OLRC在L + 1级的第二个DLC中与ILRC进行本地点对点连接。 在第二实施例中，可以从任何其他专用逻辑单元进行本地连接，无论相对于相对点或多路复用器是水平还是垂直的，以及来自当前逻辑和路由单元（LRC）的任何偏移。 在第三实施例中，可以通过将第一OLRC拼接到第二OLRC（用于连接到ILRC）来实现本地连接，这允许来自其他列或DLC级的线路到达用于快速本地互连的ILRC。

公开(公告)号：US07605605B2

公开(公告)日：2009-10-20

申请号：US11044386

申请日：2005-01-27

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.

摘要翻译： 公开了一种使用输入逻辑路由单元（ILRC）多路复用器和输出逻辑路由单元（OLRC）多路复用器进行专用逻辑单元之间的本地连接的可编程逻辑结构。 在简单的可编程逻辑结构中，专用逻辑单元（DLC）以包括用于端口A的多个ILRC多路复用器和用于端口B的多个OLRC多路复用器的可编程逻辑结构实现。在多级可编程逻辑结构中，多列专用逻辑 单元被设计成具有彼此相邻的专用本地单元的列，其中每个DLC列用于实现特定的逻辑功能。 在第一实施例中，可以在专用逻辑单元之间进行本地连接。 在L级的第一个DLC中的OLRC在L + 1级的第二个DLC中与ILRC进行本地点对点连接。 在第二实施例中，可以从任何其他专用逻辑单元进行本地连接，无论相对于相对点或多路复用器是水平还是垂直的，以及来自当前逻辑和路由单元（LRC）的任何偏移。 在第三实施例中，可以通过将第一OLRC拼接到第二OLRC（用于连接到ILRC）来实现本地连接，这允许来自其他列或DLC级的线路到达用于快速本地互连的ILRC。

公开(公告)号：US20080129334A1

公开(公告)日：2008-06-05

申请号：US12007705

申请日：2008-01-15

申请人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

发明人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

IPC分类号： H03K19/00 ,  G06F17/50

CPC分类号： H03K19/1737

摘要： Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.

公开(公告)号：US20070085564A1

公开(公告)日：2007-04-19

申请号：US11539757

申请日：2006-10-09

申请人： Hare Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

发明人： Hare Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.

摘要翻译： 公开了一种使用输入逻辑路由单元（ILRC）多路复用器和输出逻辑路由单元（OLRC）多路复用器进行专用逻辑单元之间的本地连接的可编程逻辑结构。 在简单的可编程逻辑结构中，专用逻辑单元（DLC）以包括用于端口A的多个ILRC多路复用器和用于端口B的多个OLRC多路复用器的可编程逻辑结构实现。在多级可编程逻辑结构中，多列专用逻辑 单元被设计成具有彼此相邻的专用本地单元的列，其中每个DLC列用于实现特定的逻辑功能。 在第一实施例中，可以在专用逻辑单元之间进行本地连接。 在L级的第一个DLC中的OLRC在L + 1级的第二个DLC中与ILRC进行本地点对点连接。 在第二实施例中，可以从任何其他专用逻辑单元进行本地连接，无论相对于相对点或多路复用器是水平还是垂直的，以及来自当前逻辑和路由单元（LRC）的任何偏移。 在第三实施例中，可以通过将第一OLRC拼接到第二OLRC（用于连接到ILRC）来实现本地连接，这允许来自其他列或DLC级的线路到达用于快速本地互连的ILRC。

公开(公告)号：US07728623B2

公开(公告)日：2010-06-01

申请号：US11539757

申请日：2006-10-09

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.

摘要翻译： 公开了一种使用输入逻辑路由单元（ILRC）多路复用器和输出逻辑路由单元（OLRC）多路复用器进行专用逻辑单元之间的本地连接的可编程逻辑结构。 在简单的可编程逻辑结构中，专用逻辑单元（DLC）以包括用于端口A的多个ILRC多路复用器和用于端口B的多个OLRC多路复用器的可编程逻辑结构实现。在多级可编程逻辑结构中，多列专用逻辑 单元被设计成具有彼此相邻的专用本地单元的列，其中每个DLC列用于实现特定的逻辑功能。 在第一实施例中，可以在专用逻辑单元之间进行本地连接。 在L级的第一个DLC中的OLRC在L + 1级的第二个DLC中与ILRC进行本地点对点连接。 在第二实施例中，可以从任何其他专用逻辑单元进行本地连接，无论相对于相对点或多路复用器是水平还是垂直的，以及来自当前逻辑和路由单元（LRC）的任何偏移。 在第三实施例中，可以通过将第一OLRC拼接到第二OLRC（用于连接到ILRC）来实现本地连接，这允许来自其他列或DLC级的线路到达用于快速本地互连的ILRC。

公开(公告)号：US07358761B1

公开(公告)日：2008-04-15

申请号：US11040633

申请日：2005-01-21

申请人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

发明人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

IPC分类号： H03K19/173

CPC分类号： H03K19/1737

摘要： Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.

摘要翻译： 逻辑设计装置和方法提供可编程逻辑结构中的串行复用器链，链中的每个元件选择块的输出，或者从链的早期元素传递输出。 选择行是可配置函数发生器的解码器结构或输出，在上电时配置，以创建正确的选择。 使用这种结构，可以创建更大的多路复用器，包括优先复用器，三态总线或更大的查找表（LUT）。 这些新颖的结构可以实现优先级，非优先级或三态多路复用器。