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公开(公告)号：US08995940B2
公开(公告)日：2015-03-31
申请号：US11528203
申请日：2006-09-27
申请人： Srihari Adireddy , Brian D. Green
发明人： Srihari Adireddy , Brian D. Green
CPC分类号： H04L12/66
摘要： A technique includes receiving data that is communicated in a frame over a wireless network and processing the data through a filter. A response of the filter is changed during the processing.
摘要翻译： 一种技术包括接收通过无线网络在帧中传送的数据并通过滤波器处理数据。 过滤器的响应在处理过程中发生变化。
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2.发明授权公开(公告)号：US07676210B2
公开(公告)日：2010-03-09
申请号：US11227797
申请日：2005-09-15
IPC分类号： H04B1/10
摘要： A method is disclosed for performing dual mode image rejection calibration in a receiver. A first image correction factor is acquired for use in a receiver system using a first known signal associated with a first signal band during a startup mode. The first image correction factor is adjusted incrementally during a normal operation mode. A radio frequency (RF) signal associated with the first signal band is received using the first image correction factor during the normal operation mode.
摘要翻译： 公开了一种用于在接收机中执行双模式拒绝校准的方法。 在启动模式期间，使用与第一信号频带相关联的第一已知信号在接收机系统中获取第一图像校正因子。 在正常操作模式期间，第一图像校正因子被递增地调整。 在正常操作模式期间使用第一图像校正因子接收与第一信号频带相关联的射频（RF）信号。
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3.发明授权Wireless communication system and method using clock swapping during image rejection calibration 失效无线通信系统和方法在镜像抑制校准期间使用时钟交换公开(公告)号：US07583946B2
公开(公告)日：2009-09-01
申请号：US11340941
申请日：2006-01-27
IPC分类号： H04B1/06
摘要： A wireless communication receiver is disclosed that operates in a test mode to determine image correction information that is used to suppress undesired image signals when the receiver switches to a normal operational mode. In one embodiment, the receiver includes a frequency synthesizer coupled by a quadrature divider to an in-phase (I) mixer and a quadrature mixer. The mixers are coupled by respective analog to digital converters (ADCs) to respective I and Q channel inputs of a digital signal processor (DSP). In the test mode, a test tone is provided to the mixer inputs. The test tone is divided down further and provided to clock the frequency synthesizer, the ADCs and the DSP. This configuration locks together the mixers, frequency synthesizer, ADCs and DSP ratiometrically in frequency during the test mode while image correction information is being determined. When the receiver switches to a normal operating mode, the frequency synthesizer, ADCs and DSP are clocked by a main clock signal instead of the divided down test tone, and the test tone is removed from the mixers.
摘要翻译： 公开了一种在测试模式下操作以确定当接收机切换到正常操作模式时用于抑制不期望的图像信号的图像校正信息的无线通信接收机。 在一个实施例中，接收机包括由正交分频器耦合到同相（I）混频器和正交混频器的频率合成器。 混频器由相应的模数转换器（ADC）耦合到数字信号处理器（DSP）的相应的I和Q通道输入端。 在测试模式下，向混音器输入提供测试音。 测试音被进一步分频并提供给时钟频率合成器，ADC和DSP。 该配置在确定图像校正信息期间在测试模式期间将混频器，频率合成器，ADC和DSP按比例的频率锁定在频率上。 当接收机切换到正常工作模式时，频率合成器，ADC和DSP由主时钟信号而不是分频测试音来计时，测试音从混频器中移除。
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4.发明申请公开(公告)号：US20060111071A1
公开(公告)日：2006-05-25
申请号：US11227797
申请日：2005-09-15
申请人： Tod Paulus , Donald Kerth , Srihari Adireddy , G. Vishakhadatta
发明人： Tod Paulus , Donald Kerth , Srihari Adireddy , G. Vishakhadatta
摘要： A method is disclosed for performing dual mode image rejection calibration in a receiver. A first image correction factor is acquired (1302) for use in a receiver system (15) using a first known signal associated with a first signal band during a startup mode. The first image correction factor is adjusted incrementally (1310) during a normal operation mode. A radio frequency (RF) signal associated with the first signal band is received (1324) using the first image correction factor during the normal operation mode.
摘要翻译： 公开了一种用于在接收机中执行双模式拒绝校准的方法。 在启动模式期间，使用与第一信号频带相关联的第一已知信号，在接收机系统（15）中获取第一图像校正因子（1302）。 在正常操作模式期间，第一图像校正因子被逐渐调整（1310）。 在正常操作模式期间，使用第一图像校正因子接收与第一信号频带相关联的射频（RF）信号（1324）。
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公开(公告)号：US06754294B1
公开(公告)日：2004-06-22
申请号：US09627453
申请日：2000-07-27
申请人： Srihari Adireddy , Lang Tong
发明人： Srihari Adireddy , Lang Tong
IPC分类号： H03D1104
CPC分类号： H04L25/03057 , H04L25/0228 , H04L2025/0349 , H04L2025/03617
摘要： An apparatus for reducing a precursor ISI signal in a receiver that receives an incoming stream of symbols distorted by intersymbol interference (ISI) includes: 1) a first forward filter for receiving the incoming stream of distorted symbols and generating a first equalized output signal (Y′k); 2) a first decision feedback equalizer (DFE) stage for receiving the Y′k signal and generating a first decided symbol sequence (Ŝk−d), wherein the first DFE stage generates from Ŝk−d a first postcursor cancellation signal that reduces postcursor ISI in the Y′k signal and generates from the Y′k signal a first symbol estimate signal (vk) in which postcursor ISI is at least partially reduced; and 3) a second decision feedback equalizer (DFE) stage for receiving the Y′k signal and generating a second decided symbol sequence (Ŝk−2d), wherein the second DFE stage comprises a soft symbol estimator that receives the vk signal and generates a soft decision sequence (Ŝ′k−d) comprising decided symbols and zero output signals, and wherein the second DFE stage generates from Ŝ′k−d a precursor cancellation signal that reduces precursor ISI in the Y′k signal.
摘要翻译： 一种用于减少接收器中的前体ISI信号的装置，其接收由符号间干扰（ISI）失真的进入的符号流，包括：1）第一正向滤波器，用于接收输入的失真符号流并产生第一均衡输出信号 'k）; 2）第一判决反馈均衡器（DFE）级，用于接收所述Y'k信号并产生第一确定符号序列（Sk-d），其中所述第一DFE级从Sk-d生成第一后移消除信号，其减少后置ISI 在Y'k信号中，并且从Y'k信号产生其中后端ISI至少部分减小的第一符号估计信号（vk） 以及3）第二判决反馈均衡器（DFE）级，用于接收所述Y'k信号并产生第二确定符号序列（Sk-2d），其中所述第二DFE级包括软符号估计器，所述软符号估计器接收所述vk信号并产生 软判决序列（S'k-d）包括确定的符号和零输出信号，并且其中第二DFE级从S'k-d生成减少Y'k信号中的前体ISI的前导消除信号。
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公开(公告)号：US20110134974A1
公开(公告)日：2011-06-09
申请号：US13027353
申请日：2011-02-15
CPC分类号： H04B1/40
摘要： In one embodiment, the present invention includes a transceiver coupled to a baseband processor to receive digital control information that includes both event and schedule information, and which stores the digital control information in a storage of the transceiver. The transceiver may then be operated according to the event and schedule information.
摘要翻译： 在一个实施例中，本发明包括耦合到基带处理器的收发器，以接收包括事件和时间表信息的数字控制信息，并且将数字控制信息存储在收发器的存储器中。 然后可以根据事件和进度信息来操作收发器。
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公开(公告)号：US07907657B2
公开(公告)日：2011-03-15
申请号：US11478924
申请日：2006-06-30
CPC分类号： H04B1/40
摘要： In one embodiment, the present invention includes a transceiver coupled to a baseband processor to receive digital control information that includes both event and schedule information, and which stores the digital control information in a storage of the transceiver. The transceiver may then be operated according to the event and schedule information.
摘要翻译： 在一个实施例中，本发明包括耦合到基带处理器的收发器，以接收包括事件和时间表信息的数字控制信息，并且将数字控制信息存储在收发器的存储器中。 然后可以根据事件和进度信息来操作收发器。
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8.发明申请公开(公告)号：US20060128338A1
公开(公告)日：2006-06-15
申请号：US11340941
申请日：2006-01-27
申请人： Donald Kerth , Srihari Adireddy , Brian Green , Todd Paulus , Scott Willlingham
发明人： Donald Kerth , Srihari Adireddy , Brian Green , Todd Paulus , Scott Willlingham
摘要： A wireless communication receiver is disclosed that operates in a test mode to determine image correction information that is used to suppress undesired image signals when the receiver switches to a normal operational mode. In one embodiment, the receiver includes a frequency synthesizer coupled by a quadrature divider to an in-phase (I) mixer and a quadrature mixer. The mixers are coupled by respective analog to digital converters (ADCs) to respective I and Q channel inputs of a digital signal processor (DSP). In the test mode, a test tone is provided to the mixer inputs. The test tone is divided down further and provided to clock the frequency synthesizer, the ADCs and the DSP. This configuration locks together the mixers, frequency synthesizer, ADCs and DSP ratiometrically in frequency during the test mode while image correction information is being determined. When the receiver switches to a normal operating mode, the frequency synthesizer, ADCs and DSP are clocked by a main clock signal instead of the divided down test tone, and the test tone is removed from the mixers.
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9.发明授权System and methods for precursor cancellation of intersymbol interference in a receiver 有权用于接收机中符号间干扰的前体消除的系统和方法公开(公告)号：US06912250B1
公开(公告)日：2005-06-28
申请号：US09627237
申请日：2000-07-27
申请人： Srihari Adireddy , Lang Tong
发明人： Srihari Adireddy , Lang Tong
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03726
摘要： There is disclosed, for use in a receiver receiving from a transmission channel an incoming stream of known symbols and unknown symbols distorted by intersymbol interference (ISI), an apparatus for reducing a precursor ISI signal. The apparatus for reducing the precursor ISI signal comprises: 1) a decision feedback equalizer for receiving the incoming stream of distorted known symbols and distorted unknown symbols and generating a sequence of detected symbols; and 2) a known symbol generator for generating a copy of a first known symbol prior to an estimation of the first known symbol by the decision feedback equalizer, wherein the decision feedback equalizer uses the copy of the first known symbol to reduce a first precursor ISI signal in a second symbol transmitted prior to the first known symbol.
摘要翻译： 公开了一种用于从传输信道接收已知符号的输入流和通过符号间干扰（ISI）而失真的未知符号的接收机的接收机，用于减少前体ISI信号的装置。 用于减少前体ISI信号的装置包括：1）判决反馈均衡器，用于接收失真的已知符号的输入流和失真的未知符号，并产生检测符号的序列; 以及2）已知符号发生器，用于在由所述判决反馈均衡器估计所述第一已知符号之前产生第一已知符号的副本，其中所述判决反馈均衡器使用所述第一已知符号的副本来减少第一前体ISI 在第一已知符号之前发送的第二符号中的信号。
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公开(公告)号：US07583937B2
公开(公告)日：2009-09-01
申请号：US11301521
申请日：2005-12-13
IPC分类号： H04B1/40
CPC分类号： H04B1/40
摘要： In one embodiment, the present invention includes a method for receiving at a transceiver from a baseband processor digital control information that includes both event and schedule information, storing the digital control information in a storage of the transceiver, and operating the transceiver according to the event and schedule information.
摘要翻译： 在一个实施例中，本发明包括一种用于从基带处理器接收数据控制信息的方法，所述数字控制信息包括事件和时间表信息，将数字控制信息存储在收发器的存储器中，并根据事件操作收发器 和时间表信息。
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