Processing with compact arithmetic processing element
    1.
    发明授权
    Processing with compact arithmetic processing element 有权
    使用紧凑的算术处理元件进行处理

    公开(公告)号:US09218156B2

    公开(公告)日:2015-12-22

    申请号:US13849606

    申请日:2013-03-25

    发明人: Joseph Bates

    摘要: A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).

    摘要翻译: 诸如可编程和/或大规模并行处理器或其他设备的处理器或其他设备包括被设计为执行算术运算(可能但不一定包括例如加法,乘法,减法和除法中的一个或多个)的处理元件 )对低精度但高动态范围的数值(“LPHDR算术”)。 这样的处理器或其他设备可以例如在单个芯片上实现。 无论是否在单个芯片上实现,本发明的某些实施例中的处理器或其他设备中的LPHDR算术元件的数量显着地超过(例如,至少20倍以上)算术元素的数量(如果有的话) ,在处理器或其他设备中,被设计为执行传统精度的高动态范围算术(例如32位或64位浮点运算)。

    Processing with compact arithmetic processing element

    公开(公告)号:US11842166B2

    公开(公告)日:2023-12-12

    申请号:US18073972

    申请日:2022-12-02

    发明人: Joseph Bates

    摘要: A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).